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DSP switched mode 16 and 40

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git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3045 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
nakeee
2009-04-22 19:08:13 +00:00
parent e3c4e040e9
commit 89178f411c
5 changed files with 27 additions and 26 deletions
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10
Source/Core/DSPCore/Src/DSPInterpreter.cpp
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@ -1468,7 +1468,7 @@ void srbith(const UDSPInstruction& opc)
// 15-bit precision? clamping? no idea :(
// CLR15 seems to be the default.
// nakee: It seems to come around mul operation, and it explains what sets the mul bit. But if so why not set/clr14?
// It seems to come around mul operation,
case 0xc: // CLR15
g_dsp.r[DSP_REG_SR] &= ~SR_TOP_BIT_UNK;
break;
@ -1479,12 +1479,12 @@ void srbith(const UDSPInstruction& opc)
// 40-bit precision? clamping? no idea :(
// 40 seems to be the default.
// Confirmed these by using DSPSpy and copying the value of SR to R00 after setting.
case 0xe: // SET40 (really, clear SR's 0x4000) something about "set 40-bit operation"?
g_dsp.r[DSP_REG_SR] &= ~SR_16_BIT;
case 0xe: // SET16 (really, clear SR's 0x4000)
g_dsp.r[DSP_REG_SR] &= ~SR_40_MODE_BIT;
break;
case 0xf: // SET16 (really, set SR's 0x4000) something about "set 16-bit operation"?
g_dsp.r[DSP_REG_SR] |= SR_16_BIT;
case 0xf: // SET40 (really, set SR's 0x4000)
g_dsp.r[DSP_REG_SR] |= SR_40_MODE_BIT;
break;
default:

8
Source/Core/DSPCore/Src/DSPTables.cpp
View File

@ -218,13 +218,11 @@ const DSPOPCTemplate opcodes[] =
{"M2", 0x8a00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"M0", 0x8b00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
// These guys probably change the precision or range of some operations.
// calculations or something? Or clamp?
// SET15/CLR15 is commonly used around MULXAC in Zeldas.
{"CLR15", 0x8c00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"SET15", 0x8d00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"SET40", 0x8e00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"SET16", 0x8f00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"SET16", 0x8e00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"SET40", 0x8f00, 0xffff, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},
{"INCM", 0x7400, 0xfeff, DSPInterpreter::incm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, dsp_op_ext_ops_pro, dsp_op_ext_ops_epi},

21
Source/Core/DSPCore/Src/gdsp_registers.h
View File

@ -93,15 +93,18 @@
#define DSP_STACK_D 1
#define SR_UNKNOWN 0x0002 // ????????
#define SR_ARITH_ZERO 0x0004
#define SR_SIGN 0x0008 // tested
#define SR_TOP2BITS 0x0020 // this is an odd one.
#define SR_LOGIC_ZERO 0x0040
#define SR_INT_ENABLE 0x0200 // Not 100% sure but duddie says so. This should replace the hack, if so.
#define SR_MUL_MODIFY 0x2000 // 1 = normal. 0 = x2 (M0, M2)
#define SR_TOP_BIT_UNK 0x8000 // 1 = normal. 0 = x2 (CLR15, SET15)
#define SR_16_BIT 0x4000 // 1 = "16", 0 = "40" (SET40, SET16) .. actually, seems it's the reverse. Controls sign extension when loading mid accums.
// SR bits
#define SR_CARRY 0x0001
#define SR_UNKNOWN 0x0002 // ????????
#define SR_ARITH_ZERO 0x0004
#define SR_SIGN 0x0008
#define SR_TOP2BITS 0x0020 // this is an odd one.
#define SR_LOGIC_ZERO 0x0040
#define SR_INT_ENABLE 0x0200 // Not 100% sure but duddie says so. This should replace the hack, if so.
#define SR_MUL_MODIFY 0x2000 // 1 = normal. 0 = x2 (M0, M2)
#define SR_40_MODE_BIT 0x4000 // 0 = "16", 1 = "40" (SET16, SET40) Controls sign extension when loading mid accums.
#define SR_TOP_BIT_UNK 0x8000 // 1 = normal. 0 = x2 (CLR15, SET15) ????????
void dsp_reg_store_stack(u8 stack_reg, u16 val);
u16 dsp_reg_load_stack(u8 stack_reg);