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JitArm64: Implement DSI exception.

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Ok, this falls back on all memory instructions, but it's a way to start.
This commit is contained in:
degasus
2016-05-14 11:31:17 +02:00
parent 5db61b4bbb
commit 8e902abca3
3 changed files with 24 additions and 10 deletions
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25
Source/Core/Core/PowerPC/JitArm64/Jit.cpp
View File

@ -6,6 +6,7 @@
#include "Common/Arm64Emitter.h" #include "Common/Arm64Emitter.h"
#include "Common/CommonTypes.h" #include "Common/CommonTypes.h"
#include "Common/MathUtil.h"
#include "Common/PerformanceCounter.h" #include "Common/PerformanceCounter.h"
#include "Common/StringUtil.h" #include "Common/StringUtil.h"
#include "Common/Logging/Log.h" #include "Common/Logging/Log.h"
@ -590,12 +591,6 @@ const u8* JitArm64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitB
js.firstFPInstructionFound = true; js.firstFPInstructionFound = true;
} }
if (jo.memcheck && (opinfo->flags & FL_USE_FPU))
{
// Don't do this yet
BRK(0x7777);
}
JitArm64Tables::CompileInstruction(ops[i]); JitArm64Tables::CompileInstruction(ops[i]);
// If we have a register that will never be used again, flush it. // If we have a register that will never be used again, flush it.
@ -604,8 +599,22 @@ const u8* JitArm64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitB
if (jo.memcheck && (opinfo->flags & FL_LOADSTORE)) if (jo.memcheck && (opinfo->flags & FL_LOADSTORE))
{ {
// Don't do this yet ARM64Reg WA = gpr.GetReg();
BRK(0x666); LDR(INDEX_UNSIGNED, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
FixupBranch noException = TBZ(WA, IntLog2(EXCEPTION_DSI));
FixupBranch handleException = B();
SwitchToFarCode();
SetJumpTarget(handleException);
gpr.Flush(FLUSH_MAINTAIN_STATE);
fpr.Flush(FLUSH_MAINTAIN_STATE);
WriteExceptionExit(js.compilerPC);
SwitchToNearCode();
SetJumpTarget(noException);
gpr.Unlock(WA);
} }
} }

7
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp
View File

@ -375,6 +375,7 @@ void JitArm64::lXX(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff); JITDISABLE(bJITLoadStoreOff);
FALLBACK_IF(jo.memcheck);
u32 a = inst.RA, b = inst.RB, d = inst.RD; u32 a = inst.RA, b = inst.RB, d = inst.RD;
s32 offset = inst.SIMM_16; s32 offset = inst.SIMM_16;
@ -480,6 +481,7 @@ void JitArm64::stX(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff); JITDISABLE(bJITLoadStoreOff);
FALLBACK_IF(jo.memcheck);
u32 a = inst.RA, b = inst.RB, s = inst.RS; u32 a = inst.RA, b = inst.RB, s = inst.RS;
s32 offset = inst.SIMM_16; s32 offset = inst.SIMM_16;
@ -557,7 +559,7 @@ void JitArm64::lmw(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff); JITDISABLE(bJITLoadStoreOff);
FALLBACK_IF(!jo.fastmem); FALLBACK_IF(!jo.fastmem || jo.memcheck);
u32 a = inst.RA; u32 a = inst.RA;
@ -643,7 +645,7 @@ void JitArm64::stmw(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff); JITDISABLE(bJITLoadStoreOff);
FALLBACK_IF(!jo.fastmem); FALLBACK_IF(!jo.fastmem || jo.memcheck);
u32 a = inst.RA; u32 a = inst.RA;
@ -803,6 +805,7 @@ void JitArm64::dcbz(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff); JITDISABLE(bJITLoadStoreOff);
FALLBACK_IF(jo.memcheck);
int a = inst.RA, b = inst.RB; int a = inst.RA, b = inst.RB;

2
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp
View File

@ -23,6 +23,7 @@ void JitArm64::lfXX(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreFloatingOff); JITDISABLE(bJITLoadStoreFloatingOff);
FALLBACK_IF(jo.memcheck);
u32 a = inst.RA, b = inst.RB; u32 a = inst.RA, b = inst.RB;
@ -210,6 +211,7 @@ void JitArm64::stfXX(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreFloatingOff); JITDISABLE(bJITLoadStoreFloatingOff);
FALLBACK_IF(jo.memcheck);
u32 a = inst.RA, b = inst.RB; u32 a = inst.RA, b = inst.RB;