mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2024-11-14 21:37:52 -07:00
fixed neg and added arith test
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3140 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
parent
2ca4567601
commit
90ae2a8e55
150
Source/DSPSpy/tests/arith_test.ds
Normal file
150
Source/DSPSpy/tests/arith_test.ds
Normal file
@ -0,0 +1,150 @@
|
||||
; various arithmetic tests
|
||||
incdir "tests"
|
||||
include "dsp_base.inc"
|
||||
|
||||
set40
|
||||
|
||||
clr $acc0
|
||||
tst $acc0
|
||||
|
||||
call send_back ; 1
|
||||
|
||||
clr $acc1
|
||||
tst $acc1
|
||||
|
||||
call send_back ; 2
|
||||
|
||||
set16
|
||||
tst $acc0
|
||||
set40
|
||||
|
||||
call send_back ; 3
|
||||
|
||||
lri $ac0.h, #0x1111
|
||||
lri $ac0.m, #0x0100
|
||||
lri $ac0.l, #0x0001
|
||||
lsl $acc0, #1
|
||||
|
||||
call send_back ; 4
|
||||
|
||||
lri $ac0.h, #0x1111
|
||||
lri $ac0.m, #0x0100
|
||||
lri $ac0.l, #0x0001
|
||||
asl $acc0, #1
|
||||
|
||||
call send_back ; 5
|
||||
|
||||
clr $acc0
|
||||
lri $ac0.h, #0x1111
|
||||
tst $acc0
|
||||
|
||||
call send_back ; 6
|
||||
|
||||
lri $ac0.m, #0x0100
|
||||
tst $acc0
|
||||
|
||||
call send_back ; 7
|
||||
|
||||
lri $ac0.l, #0x0001
|
||||
tst $acc0
|
||||
|
||||
call send_back ; 8
|
||||
clr $acc0
|
||||
|
||||
lri $ac0.l, #-1
|
||||
tst $acc0
|
||||
|
||||
call send_back ; 9
|
||||
|
||||
clr $acc0
|
||||
|
||||
set16
|
||||
lri $ac0.l, #-1
|
||||
tst $acc0
|
||||
set40
|
||||
|
||||
call send_back ; 10
|
||||
|
||||
clr $acc0
|
||||
lri $ac0.h, #0x1000
|
||||
tst $acc0
|
||||
|
||||
call send_back ; 11
|
||||
|
||||
clr $acc0
|
||||
lri $ac0.h, #0x0100
|
||||
tst $acc0
|
||||
|
||||
call send_back ; 12
|
||||
|
||||
|
||||
clr $acc0
|
||||
lri $ac0.h, #0x0010
|
||||
tst $acc0
|
||||
|
||||
call send_back ; 13
|
||||
|
||||
clr $acc0
|
||||
lri $ac0.h, #0x0001
|
||||
tst $acc0
|
||||
|
||||
call send_back ; 14
|
||||
|
||||
clr $acc0
|
||||
lri $ac0.l, #0x1000
|
||||
tst $acc0
|
||||
|
||||
call send_back ; 15
|
||||
|
||||
clr $acc0
|
||||
lri $ac0.l, #0x0100
|
||||
tst $acc0
|
||||
|
||||
call send_back ; 16
|
||||
|
||||
|
||||
clr $acc0
|
||||
lri $ac0.l, #0x0010
|
||||
tst $acc0
|
||||
|
||||
call send_back ; 17
|
||||
|
||||
clr $acc0
|
||||
lri $ac0.l, #0x0001
|
||||
tst $acc0
|
||||
|
||||
call send_back ; 18
|
||||
|
||||
clr $acc0
|
||||
clr $acc1
|
||||
lri $ac0.l, #0x0001
|
||||
sub $acc1, $acc0
|
||||
|
||||
call send_back ; 19
|
||||
|
||||
clr $acc0
|
||||
clr $acc1
|
||||
set16
|
||||
lri $ac0.l, #0x0001
|
||||
sub $acc1, $acc0
|
||||
set40
|
||||
|
||||
call send_back ; 20
|
||||
|
||||
clr $acc0
|
||||
clr $acc1
|
||||
lri $ac0.l, #0x0001
|
||||
lri $ac1.h, #0x8000
|
||||
sub $acc1, $acc0
|
||||
|
||||
call send_back ; 21
|
||||
|
||||
clr $acc0
|
||||
clr $acc1
|
||||
set16
|
||||
lri $ac0.l, #0x0001
|
||||
lri $ac1.h, #0x8000
|
||||
sub $acc1, $acc0
|
||||
set40
|
||||
|
||||
call send_back ; 22
|
@ -2,109 +2,115 @@
|
||||
incdir "tests"
|
||||
include "dsp_base.inc"
|
||||
|
||||
lri $ACC0, #0x0001
|
||||
lri $SR, #0x0001
|
||||
|
||||
clr $ACC0
|
||||
neg $ACC0
|
||||
|
||||
call send_back ; 1
|
||||
|
||||
|
||||
lri $ACC0, #0x0001
|
||||
lri $SR, #0x0002
|
||||
clr $ACC0
|
||||
lri $ac0.l, #0x0001
|
||||
lri $SR, #0x0001
|
||||
|
||||
neg $ACC0
|
||||
call send_back ; 2
|
||||
|
||||
lri $ACC0, #0x0001
|
||||
lri $SR, #0x0004
|
||||
|
||||
lri $ac0.l, #0x0001
|
||||
lri $SR, #0x0002
|
||||
|
||||
neg $ACC0
|
||||
call send_back ; 3
|
||||
|
||||
lri $ACC0, #0x0001
|
||||
lri $SR, #0x0008
|
||||
lri $ac0.l, #0x0001
|
||||
lri $SR, #0x0004
|
||||
|
||||
neg $ACC0
|
||||
call send_back ; 4
|
||||
|
||||
lri $ACC0, #0x0001
|
||||
lri $SR, #0x0010
|
||||
lri $ac0.l, #0x0001
|
||||
lri $SR, #0x0008
|
||||
|
||||
neg $ACC0
|
||||
call send_back ; 5
|
||||
|
||||
lri $ACC0, #0x0001
|
||||
lri $SR, #0x0020
|
||||
lri $ac0.l, #0x0001
|
||||
lri $SR, #0x0010
|
||||
|
||||
neg $ACC0
|
||||
call send_back ; 6
|
||||
|
||||
lri $ACC0, #0x0001
|
||||
lri $SR, #0x0040
|
||||
lri $ac0.l, #0x0001
|
||||
lri $SR, #0x0020
|
||||
|
||||
neg $ACC0
|
||||
call send_back ; 7
|
||||
|
||||
lri $ACC0, #0x0001
|
||||
lri $SR, #0x0080
|
||||
lri $ac0.l, #0x0001
|
||||
lri $SR, #0x0040
|
||||
|
||||
neg $ACC0
|
||||
call send_back ; 8
|
||||
|
||||
lri $ACC0, #0x0001
|
||||
lri $SR, #0x0100
|
||||
lri $ac0.l, #0x0001
|
||||
lri $SR, #0x0080
|
||||
|
||||
neg $ACC0
|
||||
call send_back ; 9
|
||||
|
||||
lri $ACC0, #0x0001
|
||||
lri $SR, #0x0200
|
||||
lri $ac0.l, #0x0001
|
||||
lri $SR, #0x0100
|
||||
|
||||
neg $ACC0
|
||||
call send_back ; 10
|
||||
|
||||
lri $ACC0, #0x0001
|
||||
lri $SR, #0x0400
|
||||
lri $ac0.l, #0x0001
|
||||
lri $SR, #0x0200
|
||||
|
||||
neg $ACC0
|
||||
call send_back ; 11
|
||||
|
||||
lri $ACC0, #0x0001
|
||||
lri $SR, #0x0800
|
||||
lri $ac0.l, #0x0001
|
||||
lri $SR, #0x0400
|
||||
|
||||
neg $ACC0
|
||||
call send_back ; 12
|
||||
|
||||
lri $ACC0, #0x0001
|
||||
lri $SR, #0x1000
|
||||
lri $ac0.l, #0x0001
|
||||
lri $SR, #0x0800
|
||||
|
||||
neg $ACC0
|
||||
call send_back ; 13
|
||||
|
||||
lri $ACC0, #0x0001
|
||||
lri $SR, #0x2000
|
||||
lri $ac0.l, #0x0001
|
||||
lri $SR, #0x1000
|
||||
|
||||
neg $ACC0
|
||||
call send_back ; 14
|
||||
|
||||
lri $ACC0, #0x0001
|
||||
lri $SR, #0x4000
|
||||
lri $ac0.l, #0x0001
|
||||
lri $SR, #0x2000
|
||||
|
||||
neg $ACC0
|
||||
call send_back ; 15
|
||||
|
||||
lri $ACC0, #0x0001
|
||||
lri $SR, #0x8000
|
||||
lri $ac0.l, #0x0001
|
||||
lri $SR, #0x4000
|
||||
|
||||
neg $ACC0
|
||||
call send_back ; 16
|
||||
|
||||
lri $ac0.l, #0x0001
|
||||
lri $SR, #0x8000
|
||||
|
||||
neg $ACC0
|
||||
call send_back ; 17
|
||||
|
||||
set16
|
||||
lri $ACC0, #0x0001
|
||||
lri $ac0.l, #0x0001
|
||||
lri $SR, #0x2230
|
||||
|
||||
neg $ACC0
|
||||
set40
|
||||
call send_back ; 17
|
||||
call send_back ; 18
|
||||
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user