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https://github.com/dolphin-emu/dolphin.git
synced 2025-07-24 14:49:42 -06:00
Core/DSPCore: Implement jit emitters for lris and mrr.
Also add the mask for ADPCM predictor, like r6480 does. Tested 64 bit linux/windows. At least compiles for 32 bit windows, but with these binaries most of my guest software fails with DSPLLE(interpreted and jit) when it gets to do actual work. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6484 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
pierre
@ -22,21 +22,306 @@
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#include "ABI.h"
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using namespace Gen;
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//clobbers:
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//EAX = (s8)g_dsp.reg_stack_ptr[stack_reg]
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//R10 = &g_dsp.reg_stack[stack_reg][0]
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//R11 = &g_dsp.r
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//CX = g_dsp.reg_stack[stack_reg][g_dsp.reg_stack_ptr[stack_reg]]
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void DSPEmitter::dsp_reg_stack_push(int stack_reg)
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{
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//g_dsp.reg_stack_ptr[stack_reg]++;
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//g_dsp.reg_stack_ptr[stack_reg] &= DSP_STACK_MASK;
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#ifdef _M_IX86 // All32
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MOV(8, R(AL), M(&g_dsp.reg_stack_ptr[stack_reg]));
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#else
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MOV(64, R(R10), ImmPtr(g_dsp.reg_stack_ptr));
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MOV(8, R(AL), MDisp(R10,stack_reg));
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#endif
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ADD(8, R(AL), Imm8(1));
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AND(8, R(AL), Imm8(DSP_STACK_MASK));
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#ifdef _M_IX86 // All32
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MOV(8, M(&g_dsp.reg_stack_ptr[stack_reg]), R(AL));
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#else
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MOV(8, MDisp(R10,stack_reg), R(AL));
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#endif
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//g_dsp.reg_stack[stack_reg][g_dsp.reg_stack_ptr[stack_reg]] = g_dsp.r[DSP_REG_ST0 + stack_reg];
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#ifdef _M_IX86 // All32
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MOV(16, R(CX), M(&g_dsp.r[DSP_REG_ST0 + stack_reg]));
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MOVZX(32, 8, EAX, R(AL));
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MOV(16, MComplex(EAX,EAX,1,(u32)&g_dsp.reg_stack[stack_reg][0]), R(CX));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOV(16, R(CX), MDisp(R11,(DSP_REG_ST0 + stack_reg)*2));
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MOVZX(64, 8, RAX, R(AL));
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MOV(64, R(R10), ImmPtr(&g_dsp.reg_stack[stack_reg][0]));
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MOV(16, MComplex(R10,RAX,2,0), R(CX));
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#endif
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}
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//clobbers:
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//EAX = (s8)g_dsp.reg_stack_ptr[stack_reg]
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//R10 = &g_dsp.reg_stack[stack_reg][0]
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//R11 = &g_dsp.r
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//CX = g_dsp.reg_stack[stack_reg][g_dsp.reg_stack_ptr[stack_reg]]
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void DSPEmitter::dsp_reg_stack_pop(int stack_reg)
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{
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//g_dsp.r[DSP_REG_ST0 + stack_reg] = g_dsp.reg_stack[stack_reg][g_dsp.reg_stack_ptr[stack_reg]];
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#ifdef _M_IX86 // All32
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MOV(8, R(AL), M(&g_dsp.reg_stack_ptr[stack_reg]));
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#else
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MOV(64, R(R10), ImmPtr(g_dsp.reg_stack_ptr));
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MOV(8, R(AL), MDisp(R10,stack_reg));
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#endif
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#ifdef _M_IX86 // All32
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MOVZX(32, 8, EAX, R(AL));
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MOV(16, R(CX), MComplex(EAX,EAX,1,(u32)&g_dsp.reg_stack[stack_reg][0]));
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MOV(16, M(&g_dsp.r[DSP_REG_ST0 + stack_reg]), R(CX));
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#else
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MOVZX(64, 8, RAX, R(AL));
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MOV(64, R(R10), ImmPtr(&g_dsp.reg_stack[stack_reg][0]));
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MOV(16, R(CX), MComplex(R10,RAX,2,0));
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOV(16, MDisp(R11,(DSP_REG_ST0 + stack_reg)*2), R(CX));
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#endif
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//g_dsp.reg_stack_ptr[stack_reg]--;
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//g_dsp.reg_stack_ptr[stack_reg] &= DSP_STACK_MASK;
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SUB(8, R(AL), Imm8(1));
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AND(8, R(AL), Imm8(DSP_STACK_MASK));
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#ifdef _M_IX86 // All32
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MOV(8, M(&g_dsp.reg_stack_ptr[stack_reg]), R(AL));
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#else
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MOV(64, R(R10), ImmPtr(g_dsp.reg_stack_ptr));
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MOV(8, MDisp(R10,stack_reg), R(AL));
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#endif
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}
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void DSPEmitter::dsp_reg_store_stack(int stack_reg, Gen::X64Reg host_sreg)
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{
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if (host_sreg != EDX) {
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MOV(16, R(EDX), R(host_sreg));
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}
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dsp_reg_stack_push(stack_reg);
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//g_dsp.r[DSP_REG_ST0 + stack_reg] = val;
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.r[DSP_REG_ST0+stack_reg]), R(EDX));
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#else
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MOV(64, R(R11), Imm64((u64)g_dsp.r));
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MOV(16, MDisp(R11,(DSP_REG_ST0+stack_reg)*2), R(EDX));
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#endif
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}
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void DSPEmitter::dsp_reg_load_stack(int stack_reg, Gen::X64Reg host_dreg)
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{
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//u16 val = g_dsp.r[DSP_REG_ST0 + stack_reg];
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#ifdef _M_IX86 // All32
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MOV(16, R(EDX), M(&g_dsp.r[DSP_REG_ST0+stack_reg]));
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#else
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MOV(64, R(R11), Imm64((u64)g_dsp.r));
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MOV(16, R(EDX), MDisp(R11,(DSP_REG_ST0+stack_reg)*2));
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#endif
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dsp_reg_stack_pop(stack_reg);
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if (host_dreg != EDX) {
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MOV(16, R(host_dreg), R(EDX));
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}
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}
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void DSPEmitter::dsp_reg_store_stack_imm(int stack_reg, u16 val)
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{
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dsp_reg_stack_push(stack_reg);
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//g_dsp.r[DSP_REG_ST0 + stack_reg] = val;
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.r[DSP_REG_ST0+stack_reg]), Imm16(val));
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#else
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MOV(64, R(R11), Imm64((u64)g_dsp.r));
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MOV(16, MDisp(R11,(DSP_REG_ST0+stack_reg)*2), Imm16(val));
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#endif
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}
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void DSPEmitter::dsp_op_write_reg(int reg, Gen::X64Reg host_sreg)
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{
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switch (reg & 0x1f) {
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// 8-bit sign extended registers. Should look at prod.h too...
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case DSP_REG_ACH0:
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case DSP_REG_ACH1:
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// sign extend from the bottom 8 bits.
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MOVSX(16,8,host_sreg,R(host_sreg));
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.r[reg]), R(host_sreg));
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#else
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MOV(64, R(R11), Imm64((u64)g_dsp.r));
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MOV(16, MDisp(R11,reg*2), R(host_sreg));
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#endif
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break;
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// Stack registers.
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case DSP_REG_ST0:
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case DSP_REG_ST1:
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case DSP_REG_ST2:
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case DSP_REG_ST3:
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dsp_reg_store_stack(reg - DSP_REG_ST0, host_sreg);
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break;
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default:
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.r[reg]), R(host_sreg));
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#else
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MOV(64, R(R11), Imm64((u64)g_dsp.r));
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MOV(16, MDisp(R11,reg*2), R(host_sreg));
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#endif
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break;
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}
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}
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void DSPEmitter::dsp_op_write_reg_imm(int reg, u16 val)
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{
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switch (reg & 0x1f) {
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// 8-bit sign extended registers. Should look at prod.h too...
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case DSP_REG_ACH0:
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case DSP_REG_ACH1:
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// sign extend from the bottom 8 bits.
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.r[reg]), Imm16((u16)(s16)(s8)(u8)val));
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#else
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MOV(64, R(R11), Imm64((u64)g_dsp.r));
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MOV(16, MDisp(R11,reg*2), Imm16((u16)(s16)(s8)(u8)val));
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#endif
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break;
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// Stack registers.
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case DSP_REG_ST0:
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case DSP_REG_ST1:
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case DSP_REG_ST2:
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case DSP_REG_ST3:
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dsp_reg_store_stack_imm(reg - DSP_REG_ST0, val);
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break;
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default:
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.r[reg]), Imm16(val));
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#else
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MOV(64, R(R11), Imm64((u64)g_dsp.r));
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MOV(16, MDisp(R11,reg*2), Imm16(val));
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#endif
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break;
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}
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}
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void DSPEmitter::dsp_conditional_extend_accum(int reg)
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{
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switch (reg)
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{
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case DSP_REG_ACM0:
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case DSP_REG_ACM1:
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{
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#ifdef _M_IX86 // All32
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MOV(16, R(EAX), M(&g_dsp.r[DSP_REG_SR]));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOV(16, R(EAX), MDisp(R11,DSP_REG_SR*2));
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#endif
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TEST(16, R(EAX), Imm16(SR_40_MODE_BIT));
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FixupBranch not_40bit = J_CC(CC_Z);
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//if (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT)
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//{
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// Sign extend into whole accum.
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//u16 val = g_dsp.r[reg];
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#ifdef _M_IX86 // All32
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MOVSX(32, 16, EAX, M(&g_dsp.r[reg]));
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#else
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MOVSX(32, 16, EAX, MDisp(R11,reg*2));
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#endif
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SHR(32,R(EAX),Imm8(16));
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//g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACH0] = (val & 0x8000) ? 0xFFFF : 0x0000;
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//g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACL0] = 0;
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#ifdef _M_IX86 // All32
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MOV(16,M(&g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACH0]),
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R(EAX));
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MOV(16,M(&g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACL0]),
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Imm16(0));
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#else
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MOV(16, MDisp(R11,(reg - DSP_REG_ACM0 + DSP_REG_ACH0)*2), R(EAX));
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MOV(16, MDisp(R11,(reg - DSP_REG_ACM0 + DSP_REG_ACL0)*2), Imm16(0));
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#endif
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//}
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SetJumpTarget(not_40bit);
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}
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}
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}
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void DSPEmitter::dsp_conditional_extend_accum_imm(int reg, u16 val)
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{
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switch (reg)
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{
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case DSP_REG_ACM0:
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case DSP_REG_ACM1:
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{
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#ifdef _M_IX86 // All32
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MOV(16, R(EAX), M(&g_dsp.r[DSP_REG_SR]));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOV(16, R(EAX), MDisp(R11,DSP_REG_SR*2));
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#endif
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TEST(16, R(EAX), Imm16(SR_40_MODE_BIT));
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FixupBranch not_40bit = J_CC(CC_Z);
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//if (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT)
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//{
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// Sign extend into whole accum.
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//g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACH0] = (val & 0x8000) ? 0xFFFF : 0x0000;
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//g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACL0] = 0;
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#ifdef _M_IX86 // All32
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MOV(16,M(&g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACH0]),
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Imm16((val & 0x8000)?0xffff:0x0000));
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MOV(16,M(&g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACL0]),
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Imm16(0));
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#else
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MOV(16, MDisp(R11,(reg - DSP_REG_ACM0 + DSP_REG_ACH0)*2),
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Imm16((val & 0x8000)?0xffff:0x0000));
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MOV(16, MDisp(R11,(reg - DSP_REG_ACM0 + DSP_REG_ACL0)*2),
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Imm16(0));
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#endif
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//}
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SetJumpTarget(not_40bit);
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}
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}
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}
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void DSPEmitter::dsp_op_read_reg(int reg, Gen::X64Reg host_dreg)
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{
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switch (reg & 0x1f) {
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case DSP_REG_ST0:
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case DSP_REG_ST1:
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case DSP_REG_ST2:
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case DSP_REG_ST3:
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return dsp_reg_load_stack(reg - 0x0c, host_dreg);
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default:
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//return g_dsp.r[reg];
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#ifdef _M_IX86 // All32
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MOV(16, R(host_dreg), M(&g_dsp.r[reg]));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOV(16, R(host_dreg), MDisp(R11,reg*2));
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#endif
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}
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}
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// MRR $D, $S
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// 0001 11dd ddds ssss
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// Move value from register $S to register $D.
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// FIXME: Perform additional operation depending on destination register.
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/*void DSPEmitter::mrr(const UDSPInstruction opc)
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void DSPEmitter::mrr(const UDSPInstruction opc)
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{
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u8 sreg = opc & 0x1f;
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u8 dreg = (opc >> 5) & 0x1f;
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u16 val = dsp_op_read_reg(sreg);
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dsp_op_write_reg(dreg, val);
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dsp_op_read_reg(sreg, EDX);
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dsp_op_write_reg(dreg, EDX);
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dsp_conditional_extend_accum(dreg);
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}
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*/
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/*
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// LRI $D, #I
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// 0000 0000 100d dddd
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// iiii iiii iiii iiii
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@ -54,18 +339,19 @@ using namespace Gen;
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dsp_op_write_reg(reg, imm);
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dsp_conditional_extend_accum(reg);
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}
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*/
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// LRIS $(0x18+D), #I
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// 0000 1ddd iiii iiii
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// Load immediate value I (8-bit sign extended) to accumulator register.
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// Load immediate value I (8-bit sign extended) to accumulator register.
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// FIXME: Perform additional operation depending on destination register.
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void DSPEmitter::lris(const UDSPInstruction opc)
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{
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u8 reg = ((opc >> 8) & 0x7) + DSP_REG_AXL0;
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u16 imm = (s8)opc;
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dsp_op_write_reg(reg, imm);
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dsp_conditional_extend_accum(reg);
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dsp_op_write_reg_imm(reg, imm);
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dsp_conditional_extend_accum_imm(reg, imm);
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}
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//----
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@ -77,9 +363,9 @@ void DSPEmitter::lris(const UDSPInstruction opc)
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// an opcode extension but not do anything. At least according to duddie.
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void DSPEmitter::nx(const UDSPInstruction opc)
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{
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zeroWriteBackLog();
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zeroWriteBackLog(opc);
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}
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*/
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//----
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// DAR $arD
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