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DSP: fixed compiler warnings and 2 crash bugs

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made the dsp_code test use our lable table rather than the table which was there before (and had few mistakes).
The other tests need to be fixed as well.



git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3063 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
nakeee
2009-04-24 14:36:31 +00:00
parent 9e427a4e59
commit 92e6d7c283
3 changed files with 206 additions and 268 deletions
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415
Source/DSPSpy/tests/dsp_code.ds
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@ -1,72 +1,9 @@
; This is the trojan program we send to the DSP from DSPSpy to figure it out.
REGS_BASE: equ 0x0f80
MEM_HI: equ 0x0f7E
MEM_LO: equ 0x0f7F
; A lot of constant definitions.
DSCR: equ 0xffc9 ; DSP DMA Control Reg
DSBL: equ 0xffcb ; DSP DMA Block Length
DSPA: equ 0xffcd ; DSP DMA DMEM Address
DSMAH: equ 0xffce ; DSP DMA Mem Address H
DSMAL: equ 0xffcf ; DSP DMA Mem Address L
ACSAH: equ 0xffd4
ACSAL: equ 0xffd5
ACEAH: equ 0xffd6
ACEAL: equ 0xffd7
ACCAH: equ 0xffd8
ACCAL: equ 0xffd9
AMDM: equ 0xffef ; ARAM DMA Request Mask
DIRQ: equ 0xfffb ; DSP Irq Request
DMBH: equ 0xfffc ; DSP Mailbox H
DMBL: equ 0xfffd ; DSP Mailbox L
CMBH: equ 0xfffe ; CPU Mailbox H
CMBL: equ 0xffff ; CPU Mailbox L
R00: equ 0x00
R01: equ 0x01
R02: equ 0x02
R03: equ 0x03
R04: equ 0x04
R05: equ 0x05
R06: equ 0x06
R07: equ 0x07
R08: equ 0x08
R09: equ 0x09
R0A: equ 0x0a
R0B: equ 0x0b
R0C: equ 0x0c
R0D: equ 0x0d
R0E: equ 0x0e
R0F: equ 0x0f
R10: equ 0x10
R11: equ 0x11
R12: equ 0x12
R13: equ 0x13
R14: equ 0x14
R15: equ 0x15
R16: equ 0x16
R17: equ 0x17
R18: equ 0x18
R19: equ 0x19
R1A: equ 0x1a
R1B: equ 0x1b
R1C: equ 0x1c
R1D: equ 0x1d
R1E: equ 0x1e
R1F: equ 0x1f
ACH0: equ 0x10
ACH1: equ 0x11
ACL0: equ 0x1e
ACL1: equ 0x1f
DSP_CR_IMEM: equ 2
DSP_CR_TO_CPU: equ 1
REGS_BASE: equ 0x0f80
MEM_HI: equ 0x0f7E
MEM_LO: equ 0x0f7F
;
; CODE STARTS HERE.
; Interrupt vectors 8 vectors, 2 opcodes each
@ -104,17 +41,17 @@ main:
si @DIRQ, #0x0001
call wait_for_cpu_mbox
lrs $ACL0, @CMBL
andi $acl1, #0x7fff
lrs $AC0.M, @CMBL
andi $ac1.m, #0x7fff
sr @MEM_HI, $ACL1
sr @MEM_LO, $ACL0
sr @MEM_HI, $AC1.M
sr @MEM_LO, $AC0.M
lri $r18, #0
lri $r19, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
lri $r1a, #0x2000
lr $r1c, @MEM_HI
lr $r1e, @MEM_LO
lri $ax0.l, #0
lri $ax1.l, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
lri $ax0.h, #0x2000
lr $ac0.l, @MEM_HI
lr $ac0.m, @MEM_LO
call do_dma
@ -126,54 +63,54 @@ main:
si @DIRQ, #0x0001
call wait_for_cpu_mbox
lrs $ACL0, @CMBL
andi $acl1, #0x7fff
lrs $AC0.M, @CMBL
andi $ac1.m, #0x7fff
sr @MEM_HI, $ACL1
sr @MEM_LO, $ACL0
sr @MEM_HI, $AC1.M
sr @MEM_LO, $AC0.M
lri $r18, #REGS_BASE
lri $r19, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
lri $r1a, #0x80
lr $r1c, @MEM_HI
lr $r1e, @MEM_LO
lri $ax0.l, #REGS_BASE
lri $ax1.l, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
lri $ax0.h, #0x80
lr $ac0.l, @MEM_HI
lr $ac0.m, @MEM_LO
call do_dma
; Read in all the registers from RAM
lri $r00, #REGS_BASE+1
lrri $r01, @$r00
lrri $r02, @$r00
lrri $r03, @$r00
lrri $r04, @$r00
lrri $r05, @$r00
lrri $r06, @$r00
lrri $r07, @$r00
lrri $r08, @$r00
lrri $r09, @$r00
lrri $r0a, @$r00
lrri $r0b, @$r00
lrri $r0c, @$r00
lrri $r0d, @$r00
lrri $r0e, @$r00
lrri $r0f, @$r00
lrri $r10, @$r00
lrri $r11, @$r00
lrri $r12, @$r00
lrri $r13, @$r00
lrri $r14, @$r00
lrri $r15, @$r00
lrri $r16, @$r00
lrri $r17, @$r00
lrri $r18, @$r00
lrri $r19, @$r00
lrri $r1a, @$r00
lrri $r1b, @$r00
lrri $r1c, @$r00
lrri $r1d, @$r00
lrri $r1e, @$r00
lrri $r1f, @$r00
lr $r00, @REGS_BASE
lri $ar0, #REGS_BASE+1
lrri $ar1, @$ar0
lrri $ar2, @$ar0
lrri $ar3, @$ar0
lrri $ix0, @$ar0
lrri $ix1, @$ar0
lrri $ix2, @$ar0
lrri $ix3, @$ar0
lrri $r08, @$ar0
lrri $r09, @$ar0
lrri $r10, @$ar0
lrri $r11, @$ar0
lrri $st0, @$ar0
lrri $st1, @$ar0
lrri $st2, @$ar0
lrri $st3, @$ar0
lrri $ac0.h, @$ar0
lrri $ac1.h, @$ar0
lrri $cr, @$ar0
lrri $sr, @$ar0
lrri $prod.l, @$ar0
lrri $prod.m1, @$ar0
lrri $prod.h, @$ar0
lrri $prod.m2, @$ar0
lrri $ax0.l, @$ar0
lrri $ax1.l, @$ar0
lrri $ax0.h, @$ar0
lrri $ax1.h, @$ar0
lrri $ac0.l, @$ar0
lrri $ac1.l, @$ar0
lrri $ac0.m, @$ar0
lrri $ac1.m, @$ar0
lr $ar0, @REGS_BASE
; Right here we are at a specific predetermined state.
; Ideal environment to try instructions.
@ -189,7 +126,7 @@ main:
lris $AC1.M, #0xcc
nop
mrr $r00, $r13
mrr $ar0, $sr
call send_back
set40
@ -198,7 +135,7 @@ main:
lris $AC1.M, #0xcc
nop
nop
mrr $r00, $r13
mrr $ar0, $sr
call send_back
cw 0xa100
@ -454,60 +391,60 @@ dead_loop:
jmp dead_loop
; Utility function to do DMA.
; r1c:r1e - external address.
; r18 - address in DSP
; ac0.l:ac0.m - external address.
; ax0.l - address in DSP
do_dma:
sr @DSMAH, $r1c
sr @DSMAL, $r1e
sr @DSPA, $r18
sr @DSCR, $r19
sr @DSBL, $r1a ; This kicks off the DMA.
sr @DSMAH, $ac0.l
sr @DSMAL, $ac0.m
sr @DSPA, $ax0.l
sr @DSCR, $ax1.l
sr @DSBL, $ax0.h ; This kicks off the DMA.
; Waits for said DMA to complete by watching a bit in DSCR.
wait_dma:
LRS $ACL1, @DSCR
andcf $acl1, #0x0004
LRS $AC1.M, @DSCR
andcf $ac1.m, #0x0004
JLZ wait_dma
RET
; This waits for a mail to arrive in the DSP in-mailbox.
wait_for_dsp_mbox:
lrs $ACL1, @DMBH
andcf $acl1, #0x8000
lrs $AC1.M, @DMBH
andcf $ac1.m, #0x8000
jlz wait_for_dsp_mbox
ret
; This waits for the CPU to grab a mail that we just sent from the DSP.
wait_for_cpu_mbox:
lrs $ACL1, @cmbh
andcf $acl1, #0x8000
lrs $AC1.M, @cmbh
andcf $ac1.m, #0x8000
jlnz wait_for_cpu_mbox
ret
; IRQ handlers. Not entirely sure what good they do currently.
irq0:
lri $acl0, #0x0000
lri $ac0.m, #0x0000
jmp irq
irq1:
lri $acl0, #0x0001
lri $ac0.m, #0x0001
jmp irq
irq2:
lri $acl0, #0x0002
lri $ac0.m, #0x0002
jmp irq
irq3:
lri $acl0, #0x0003
lri $ac0.m, #0x0003
jmp irq
irq4:
lri $acl0, #0x0004
lri $ac0.m, #0x0004
jmp irq
irq5:
; No idea what this code is doing.
set16
mrr $r0d, $r1c
mrr $r0d, $r1e
mrr $st1, $ac0.l
mrr $st1, $ac0.m
clr $acc0
mrr $r1e, $r0d
mrr $r1c, $r0d
mrr $ac0.m, $st1
mrr $ac0.l, $st1
nop ; Or why there's a nop sled here.
nop
nop
@ -516,22 +453,22 @@ irq5:
nop
rti
lri $acl0, #0x0005
lri $ac0.m, #0x0005
jmp irq
irq6:
lri $acl0, #0x0006
lri $ac0.m, #0x0006
jmp irq
irq7:
lri $acl0, #0x0007
lri $ac0.m, #0x0007
jmp irq
irq:
lrs $ACL1, @DMBH
andcf $acl1, #0x8000
lrs $AC1.M, @DMBH
andcf $ac1.m, #0x8000
jlz irq
si @DMBH, #0x8BAD
sr @DMBL, $r0b
;sr @DMBL, $acl0
sr @DMBL, $r11
;sr @DMBL, $ac0.m
si @DIRQ, #0x0001
halt
@ -541,56 +478,56 @@ send_back:
; make state safe.
set16
; store registers to reg table
sr @REGS_BASE, $r00
lri $r00, #(REGS_BASE + 1)
srri @$r00, $r01
srri @$r00, $r02
srri @$r00, $r03
srri @$r00, $r04
srri @$r00, $r05
srri @$r00, $r06
srri @$r00, $r07
srri @$r00, $r08
srri @$r00, $r09
srri @$r00, $r0a
srri @$r00, $r0b
srri @$r00, $r0c
srri @$r00, $r0d
srri @$r00, $r0e
srri @$r00, $r0f
srri @$r00, $r10
srri @$r00, $r11
srri @$r00, $r12
srri @$r00, $r13
srri @$r00, $r14
srri @$r00, $r15
srri @$r00, $r16
srri @$r00, $r17
srri @$r00, $r18
srri @$r00, $r19
srri @$r00, $r1a
srri @$r00, $r1b
srri @$r00, $r1c
srri @$r00, $r1d
srri @$r00, $r1e
srri @$r00, $r1f
sr @REGS_BASE, $ar0
lri $ar0, #(REGS_BASE + 1)
srri @$ar0, $ar1
srri @$ar0, $ar2
srri @$ar0, $ar3
srri @$ar0, $ix0
srri @$ar0, $ix1
srri @$ar0, $ix2
srri @$ar0, $ix3
srri @$ar0, $r08
srri @$ar0, $r09
srri @$ar0, $r10
srri @$ar0, $r11
srri @$ar0, $st0
srri @$ar0, $st1
srri @$ar0, $st2
srri @$ar0, $st3
srri @$ar0, $ac0.h
srri @$ar0, $ac1.h
srri @$ar0, $cr
srri @$ar0, $sr
srri @$ar0, $prod.l
srri @$ar0, $prod.m1
srri @$ar0, $prod.h
srri @$ar0, $prod.m2
srri @$ar0, $ax0.l
srri @$ar0, $ax1.l
srri @$ar0, $ax0.h
srri @$ar0, $ax1.h
srri @$ar0, $ac0.l
srri @$ar0, $ac1.l
srri @$ar0, $ac0.m
srri @$ar0, $ac1.m
; Regs are stored. Prepare DMA.
lri $r18, #0x0000
lri $r19, #1 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
lri $r1a, #0x200
lr $r1c, @MEM_HI
lr $r1e, @MEM_LO
lri $ax0.l, #0x0000
lri $ax1.l, #1 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
lri $ax0.h, #0x200
lr $ac0.l, @MEM_HI
lr $ac0.m, @MEM_LO
lri $r01, #8+8
lri $ar1, #8+8
; Now, why are we looping here?
bloop $r01, dma_copy
bloop $ar1, dma_copy
call do_dma
addi $r1e, #0x200
mrr $r1f, $r18
addi $r1f, #0x100
mrr $r18, $r1f
addi $ac0.m, #0x200
mrr $ac1.m, $ax0.l
addi $ac1.m, #0x100
mrr $ax0.l, $ac1.m
nop
dma_copy:
@ -604,43 +541,43 @@ dma_copy:
; wait for the CPU to recieve our response before we execute the next op
call wait_for_cpu_mbox
lrs $ACL0, @CMBL
andi $acl1, #0x7fff
lrs $AC0.M, @CMBL
andi $ac1.m, #0x7fff
; Restore all regs again so we're ready to execute another op.
lri $r00, #REGS_BASE+1
lrri $r01, @$r00
lrri $r02, @$r00
lrri $r03, @$r00
lrri $r04, @$r00
lrri $r05, @$r00
lrri $r06, @$r00
lrri $r07, @$r00
lrri $r08, @$r00
lrri $r09, @$r00
lrri $r0a, @$r00
lrri $r0b, @$r00
lrri $r0c, @$r00
lrri $r0d, @$r00
lrri $r0e, @$r00
lrri $r0f, @$r00
lrri $r10, @$r00
lrri $r11, @$r00
lrri $r12, @$r00
lrri $r13, @$r00
lrri $r14, @$r00
lrri $r15, @$r00
lrri $r16, @$r00
lrri $r17, @$r00
lrri $r18, @$r00
lrri $r19, @$r00
lrri $r1a, @$r00
lrri $r1b, @$r00
lrri $r1c, @$r00
lrri $r1d, @$r00
lrri $r1e, @$r00
lrri $r1f, @$r00
lr $r00, @REGS_BASE
lri $ar0, #REGS_BASE+1
lrri $ar1, @$ar0
lrri $ar2, @$ar0
lrri $ar3, @$ar0
lrri $ix0, @$ar0
lrri $ix1, @$ar0
lrri $ix2, @$ar0
lrri $ix3, @$ar0
lrri $r08, @$ar0
lrri $r09, @$ar0
lrri $r10, @$ar0
lrri $r11, @$ar0
lrri $st0, @$ar0
lrri $st1, @$ar0
lrri $st2, @$ar0
lrri $st3, @$ar0
lrri $ac0.h, @$ar0
lrri $ac1.h, @$ar0
lrri $cr, @$ar0
lrri $sr, @$ar0
lrri $prod.l, @$ar0
lrri $prod.m1, @$ar0
lrri $prod.h, @$ar0
lrri $prod.m2, @$ar0
lrri $ax0.l, @$ar0
lrri $ax1.l, @$ar0
lrri $ax0.h, @$ar0
lrri $ax1.h, @$ar0
lrri $ac0.l, @$ar0
lrri $ac1.l, @$ar0
lrri $ac0.m, @$ar0
lrri $ac1.m, @$ar0
lr $ar0, @REGS_BASE
ret ; from send_back
@ -652,23 +589,23 @@ send_back_40:
set40
ret
; This one's odd. Doesn't look like it should work since it uses acl0 but
; This one's odd. Doesn't look like it should work since it uses ac0.m but
; increments acm0... (acc0)
dump_memory:
lri $r02, #0x0000
lri $acl0, #0x1000
lri $ar2, #0x0000
lri $ac0.m, #0x1000
lri $r01, #0x1000
bloop $r01, _fill_loop2
lri $ar1, #0x1000
bloop $ar1, _fill_loop2
mrr $r03, $acl0
mrr $ar3, $ac0.m
nx'ld : $AX0.H, $AX1.H, @$AR0
mrr $r1f, $r00
mrr $r00, $r02
srri @$r00, $r1b
mrr $r02, $r00
mrr $r00, $r1f
mrr $ac1.m, $ar0
mrr $ar0, $ar2
srri @$ar0, $ax1.h
mrr $ar2, $ar0
mrr $ar0, $ac1.m
addis $acc0, #0x1