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JitArm64_LoadStore: Use ScopedARM64Reg
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@ -538,9 +538,12 @@ void JitArm64::lmw(UGeckoInstruction inst)
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else
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else
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ADDI2R(addr_reg, gpr.R(a), offset, addr_reg);
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ADDI2R(addr_reg, gpr.R(a), offset, addr_reg);
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ARM64Reg addr_base_reg = a_is_addr_base_reg ? ARM64Reg::INVALID_REG : gpr.GetReg();
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Arm64RegCache::ScopedARM64Reg addr_base_reg;
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if (!a_is_addr_base_reg)
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if (!a_is_addr_base_reg)
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{
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addr_base_reg = gpr.GetScopedReg();
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MOV(addr_base_reg, addr_reg);
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MOV(addr_base_reg, addr_reg);
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}
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BitSet32 gprs_to_discard{};
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BitSet32 gprs_to_discard{};
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if (!jo.memcheck)
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if (!jo.memcheck)
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@ -628,8 +631,6 @@ void JitArm64::lmw(UGeckoInstruction inst)
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gpr.Unlock(ARM64Reg::W1, ARM64Reg::W30);
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gpr.Unlock(ARM64Reg::W1, ARM64Reg::W30);
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if (jo.memcheck || !jo.fastmem)
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if (jo.memcheck || !jo.fastmem)
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gpr.Unlock(ARM64Reg::W0);
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gpr.Unlock(ARM64Reg::W0);
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if (!a_is_addr_base_reg)
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gpr.Unlock(addr_base_reg);
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}
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}
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void JitArm64::stmw(UGeckoInstruction inst)
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void JitArm64::stmw(UGeckoInstruction inst)
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@ -655,9 +656,12 @@ void JitArm64::stmw(UGeckoInstruction inst)
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else
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else
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ADDI2R(addr_reg, gpr.R(a), offset, addr_reg);
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ADDI2R(addr_reg, gpr.R(a), offset, addr_reg);
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ARM64Reg addr_base_reg = a_is_addr_base_reg ? ARM64Reg::INVALID_REG : gpr.GetReg();
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Arm64GPRCache::ScopedARM64Reg addr_base_reg;
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if (!a_is_addr_base_reg)
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if (!a_is_addr_base_reg)
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{
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addr_base_reg = gpr.GetScopedReg();
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MOV(addr_base_reg, addr_reg);
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MOV(addr_base_reg, addr_reg);
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}
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BitSet32 gprs_to_discard{};
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BitSet32 gprs_to_discard{};
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if (!jo.memcheck)
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if (!jo.memcheck)
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@ -748,8 +752,6 @@ void JitArm64::stmw(UGeckoInstruction inst)
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gpr.Unlock(ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::W30);
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gpr.Unlock(ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::W30);
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if (!jo.fastmem)
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if (!jo.fastmem)
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gpr.Unlock(ARM64Reg::W0);
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gpr.Unlock(ARM64Reg::W0);
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if (!a_is_addr_base_reg)
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gpr.Unlock(addr_base_reg);
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}
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}
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void JitArm64::dcbx(UGeckoInstruction inst)
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void JitArm64::dcbx(UGeckoInstruction inst)
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@ -786,8 +788,8 @@ void JitArm64::dcbx(UGeckoInstruction inst)
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// bdnz afterwards! So if we invalidate a single cache line, we don't adjust the registers at
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// bdnz afterwards! So if we invalidate a single cache line, we don't adjust the registers at
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// all, if we invalidate 2 cachelines we adjust the registers by one step, and so on.
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// all, if we invalidate 2 cachelines we adjust the registers by one step, and so on.
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const ARM64Reg reg_cycle_count = gpr.GetReg();
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const auto reg_cycle_count = gpr.GetScopedReg();
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const ARM64Reg reg_downcount = gpr.GetReg();
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const auto reg_downcount = gpr.GetScopedReg();
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// Figure out how many loops we want to do.
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// Figure out how many loops we want to do.
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const u8 cycle_count_per_loop =
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const u8 cycle_count_per_loop =
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@ -855,12 +857,9 @@ void JitArm64::dcbx(UGeckoInstruction inst)
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SetJumpTarget(branch_out);
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SetJumpTarget(branch_out);
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SetJumpTarget(branch_over);
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SetJumpTarget(branch_over);
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}
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}
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gpr.Unlock(reg_cycle_count, reg_downcount);
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}
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}
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constexpr ARM64Reg effective_addr = WB;
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constexpr ARM64Reg effective_addr = WB;
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const ARM64Reg physical_addr = gpr.GetReg();
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if (a)
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if (a)
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ADD(effective_addr, gpr.R(a), gpr.R(b));
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ADD(effective_addr, gpr.R(a), gpr.R(b));
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@ -874,6 +873,8 @@ void JitArm64::dcbx(UGeckoInstruction inst)
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ADD(gpr.R(b), gpr.R(b), WA, ArithOption(WA, ShiftType::LSL, 5)); // Rb += (WA * 32)
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ADD(gpr.R(b), gpr.R(b), WA, ArithOption(WA, ShiftType::LSL, 5)); // Rb += (WA * 32)
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}
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}
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auto physical_addr = gpr.GetScopedReg();
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// Translate effective address to physical address.
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// Translate effective address to physical address.
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const u8* loop_start = GetCodePtr();
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const u8* loop_start = GetCodePtr();
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FixupBranch bat_lookup_failed;
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FixupBranch bat_lookup_failed;
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@ -939,7 +940,7 @@ void JitArm64::dcbx(UGeckoInstruction inst)
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SwitchToNearCode();
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SwitchToNearCode();
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SetJumpTarget(near_addr);
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SetJumpTarget(near_addr);
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gpr.Unlock(WA, WB, physical_addr);
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gpr.Unlock(WA, WB);
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if (make_loop)
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if (make_loop)
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gpr.Unlock(loop_counter);
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gpr.Unlock(loop_counter);
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}
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}
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