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https://github.com/dolphin-emu/dolphin.git
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LLE JIT: Added the loop instructions to the JIT. Added ASM version of HandleLoop. Both x86 and x64 versions have been added.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6659 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
skidau
@ -284,3 +284,216 @@ void DSPEmitter::callr(const UDSPInstruction opc)
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{
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ReJitConditional<r_callr>(opc, *this);
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}
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// LOOP handling: Loop stack is used to control execution of repeated blocks of
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// instructions. Whenever there is value on stack $st2 and current PC is equal
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// value at $st2, then value at stack $st3 is decremented. If value is not zero
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// then PC is modified with value from call stack $st0. Otherwise values from
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// call stack $st0 and both loop stacks $st2 and $st3 are popped and execution
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// continues at next opcode.
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void DSPEmitter::HandleLoop()
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{
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, EAX, M(&(g_dsp.r[DSP_REG_ST2])));
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MOVZX(32, 16, ECX, M(&(g_dsp.r[DSP_REG_ST3])));
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#else
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MOV(64, R(R11), ImmPtr(&g_dsp.r));
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MOVZX(32, 16, EAX, MDisp(R11,DSP_REG_ST2*2));
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MOVZX(32, 16, ECX, MDisp(R11,DSP_REG_ST3*2));
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#endif
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CMP(32, R(RCX), Imm32(0));
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FixupBranch rLoopCntG = J_CC(CC_LE, true);
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CMP(16, R(RAX), Imm16(compilePC - 1));
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FixupBranch rLoopAddrG = J_CC(CC_NE, true);
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#ifdef _M_IX86 // All32
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SUB(16, M(&(g_dsp.r[DSP_REG_ST3])), Imm16(1));
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CMP(16, M(&(g_dsp.r[DSP_REG_ST3])), Imm16(0));
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#else
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SUB(16, MDisp(R11,DSP_REG_ST3*2), Imm16(1));
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CMP(16, MDisp(R11,DSP_REG_ST3*2), Imm16(0));
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#endif
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FixupBranch loadStack = J_CC(CC_LE, true);
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, ECX, M(&(g_dsp.r[DSP_REG_ST0])));
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MOV(16, M(&g_dsp.pc), R(RCX));
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#else
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MOVZX(32, 16, RCX, MDisp(R11,DSP_REG_ST0*2));
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MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
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MOV(16, MatR(RAX), R(RCX));
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#endif
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FixupBranch loopUpdated = J(true);
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SetJumpTarget(loadStack);
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dsp_reg_load_stack(0);
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dsp_reg_load_stack(2);
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dsp_reg_load_stack(3);
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SetJumpTarget(loopUpdated);
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SetJumpTarget(rLoopAddrG);
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SetJumpTarget(rLoopCntG);
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}
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// LOOP $R
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// 0000 0000 010r rrrr
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// Repeatedly execute following opcode until counter specified by value
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// from register $R reaches zero. Each execution decrement counter. Register
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// $R remains unchanged. If register $R is set to zero at the beginning of loop
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// then looped instruction will not get executed.
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// Actually, this instruction simply prepares the loop stacks for the above.
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// The looping hardware takes care of the rest.
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void DSPEmitter::loop(const UDSPInstruction opc)
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{
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u16 reg = opc & 0x1f;
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// u16 cnt = g_dsp.r[reg];
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, EDX, M(&(g_dsp.r[reg])));
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#else
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MOV(64, R(R11), ImmPtr(&g_dsp.r));
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MOVZX(32, 16, EDX, MDisp(R11,reg*2));
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#endif
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u16 loop_pc = compilePC + 1;
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CMP(16, R(EDX), Imm16(0));
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FixupBranch cnt = J_CC(CC_Z, true);
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dsp_reg_store_stack(3);
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MOV(16, R(RDX), Imm16(compilePC + 1));
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dsp_reg_store_stack(0);
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MOV(16, R(RDX), Imm16(loop_pc));
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dsp_reg_store_stack(2);
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SetJumpTarget(cnt);
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#ifdef _M_IX86 // All32
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MOV(16, M(&(g_dsp.pc)), Imm16(compilePC + 1));
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#else
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MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
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MOV(16, MDisp(RAX,0), Imm16(compilePC + 1));
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#endif
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}
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// LOOPI #I
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// 0001 0000 iiii iiii
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// Repeatedly execute following opcode until counter specified by
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// immediate value I reaches zero. Each execution decrement counter. If
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// immediate value I is set to zero at the beginning of loop then looped
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// instruction will not get executed.
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// Actually, this instruction simply prepares the loop stacks for the above.
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// The looping hardware takes care of the rest.
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void DSPEmitter::loopi(const UDSPInstruction opc)
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{
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u16 cnt = opc & 0xff;
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u16 loop_pc = compilePC + 1;
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if (cnt)
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{
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MOV(16, R(RDX), Imm16(compilePC + 1));
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dsp_reg_store_stack(0);
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MOV(16, R(RDX), Imm16(loop_pc));
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dsp_reg_store_stack(2);
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MOV(16, R(RDX), Imm16(cnt));
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dsp_reg_store_stack(3);
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#ifdef _M_IX86 // All32
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MOV(16, M(&(g_dsp.pc)), Imm16(compilePC + 1));
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#else
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MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
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MOV(16, MDisp(RAX,0), Imm16(compilePC + 1));
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#endif
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}
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}
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// BLOOP $R, addrA
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// 0000 0000 011r rrrr
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// aaaa aaaa aaaa aaaa
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// Repeatedly execute block of code starting at following opcode until
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// counter specified by value from register $R reaches zero. Block ends at
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// specified address addrA inclusive, ie. opcode at addrA is the last opcode
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// included in loop. Counter is pushed on loop stack $st3, end of block address
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// is pushed on loop stack $st2 and repeat address is pushed on call stack $st0.
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// Up to 4 nested loops are allowed.
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void DSPEmitter::bloop(const UDSPInstruction opc)
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{
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u16 reg = opc & 0x1f;
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// u16 cnt = g_dsp.r[reg];
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, EDX, M(&(g_dsp.r[reg])));
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#else
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MOV(64, R(R11), ImmPtr(&g_dsp.r));
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MOVZX(32, 16, EDX, MDisp(R11,reg*2));
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#endif
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u16 loop_pc = dsp_imem_read(compilePC + 1);
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CMP(16, R(EDX), Imm16(0));
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FixupBranch cnt = J_CC(CC_Z, true);
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dsp_reg_store_stack(3);
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MOV(16, R(RDX), Imm16(compilePC + 2));
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dsp_reg_store_stack(0);
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MOV(16, R(RDX), Imm16(loop_pc));
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dsp_reg_store_stack(2);
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#ifdef _M_IX86 // All32
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MOV(16, M(&(g_dsp.pc)), Imm16(compilePC + 2));
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#else
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MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
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MOV(16, MDisp(RAX,0), Imm16(compilePC + 2));
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#endif
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FixupBranch exit = J();
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SetJumpTarget(cnt);
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// g_dsp.pc = loop_pc;
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// dsp_skip_inst();
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.pc), Imm16(loop_pc + opTable[loop_pc]->size));
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#else
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MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
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MOV(16, MatR(RAX), Imm16(loop_pc + opTable[loop_pc]->size));
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#endif
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SetJumpTarget(exit);
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}
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// BLOOPI #I, addrA
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// 0001 0001 iiii iiii
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// aaaa aaaa aaaa aaaa
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// Repeatedly execute block of code starting at following opcode until
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// counter specified by immediate value I reaches zero. Block ends at specified
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// address addrA inclusive, ie. opcode at addrA is the last opcode included in
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// loop. Counter is pushed on loop stack $st3, end of block address is pushed
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// on loop stack $st2 and repeat address is pushed on call stack $st0. Up to 4
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// nested loops are allowed.
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void DSPEmitter::bloopi(const UDSPInstruction opc)
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{
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u16 cnt = opc & 0xff;
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// u16 loop_pc = dsp_fetch_code();
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u16 loop_pc = dsp_imem_read(compilePC + 1);
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if (cnt)
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{
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MOV(16, R(RDX), Imm16(compilePC + 2));
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dsp_reg_store_stack(0);
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MOV(16, R(RDX), Imm16(loop_pc));
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dsp_reg_store_stack(2);
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MOV(16, R(RDX), Imm16(cnt));
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dsp_reg_store_stack(3);
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#ifdef _M_IX86 // All32
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MOV(16, M(&(g_dsp.pc)), Imm16(compilePC + 2));
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#else
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MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
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MOV(16, MDisp(RAX,0), Imm16(compilePC + 2));
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#endif
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}
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else
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{
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// g_dsp.pc = loop_pc;
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// dsp_skip_inst();
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#ifdef _M_IX86 // All32
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MOV(16, M(&g_dsp.pc), Imm16(loop_pc + opTable[loop_pc]->size));
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#else
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MOV(64, R(RAX), ImmPtr(&(g_dsp.pc)));
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MOV(16, MatR(RAX), Imm16(loop_pc + opTable[loop_pc]->size));
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#endif
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}
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}
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