Merge pull request #12249 from Sintendo/frsqrte-nit

PowerPC: Negate m_dec values in frsqrte table
This commit is contained in:
Tilka
2023-10-28 02:15:05 +01:00
committed by GitHub
3 changed files with 14 additions and 15 deletions

View File

@ -150,14 +150,13 @@ void CommonAsmRoutines::GenFrsqrte()
AND(32, R(RSCRATCH), Imm32(0x7FF));
IMUL(32, RSCRATCH,
MComplex(RSCRATCH2, RSCRATCH_EXTRA, SCALE_8, offsetof(Common::BaseAndDec, m_dec)));
MOV(32, R(RSCRATCH_EXTRA),
ADD(32, R(RSCRATCH),
MComplex(RSCRATCH2, RSCRATCH_EXTRA, SCALE_8, offsetof(Common::BaseAndDec, m_base)));
SUB(32, R(RSCRATCH_EXTRA), R(RSCRATCH));
SHL(64, R(RSCRATCH_EXTRA), Imm8(26));
SHL(64, R(RSCRATCH), Imm8(26));
POP(RSCRATCH2);
OR(64, R(RSCRATCH2), R(RSCRATCH_EXTRA)); // vali |= (s64)(frsqrte_expected_base[index] -
// frsqrte_expected_dec[index] * (i % 2048)) << 26;
OR(64, R(RSCRATCH2), R(RSCRATCH)); // vali |= (s64)(frsqrte_expected_base[index] +
// frsqrte_expected_dec[index] * (i % 2048)) << 26;
MOVQ_xmm(XMM0, R(RSCRATCH2));
RET();

View File

@ -347,7 +347,7 @@ void JitArm64::GenerateFrsqrte()
LDP(IndexType::Signed, ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::X2, 0);
UBFX(ARM64Reg::X3, ARM64Reg::X3, 37, 11);
AND(ARM64Reg::X0, ARM64Reg::X0, LogicalImm(Common::DOUBLE_SIGN | Common::DOUBLE_EXP, 64));
MSUB(ARM64Reg::W3, ARM64Reg::W3, ARM64Reg::W2, ARM64Reg::W1);
MADD(ARM64Reg::W3, ARM64Reg::W3, ARM64Reg::W2, ARM64Reg::W1);
ORR(ARM64Reg::X0, ARM64Reg::X0, ARM64Reg::X3, ArithOption(ARM64Reg::X3, ShiftType::LSL, 26));
RET();