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LLE JIT: Completed the remaining JIT DSP instructions (lrrn, srrn, ilrrn).

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git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6675 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
skidau
2010-12-28 00:42:00 +00:00
parent 677fd7c052
commit 9cc19447a9
4 changed files with 56 additions and 47 deletions
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86
Source/Core/DSPCore/Src/Jit/DSPJitLoadStore.cpp
View File

@ -124,11 +124,6 @@ void DSPEmitter::lrr(const UDSPInstruction opc)
u8 dreg = opc & 0x1f;
dsp_op_read_reg(sreg, ECX);
#ifdef _M_IX86 // All32
MOVZX(32, 16, ECX, R(ECX));
#else
MOVZX(64, 16, ECX, R(ECX));
#endif
dmem_read();
dsp_op_write_reg(dreg, EAX);
dsp_conditional_extend_accum(dreg);
@ -145,11 +140,6 @@ void DSPEmitter::lrrd(const UDSPInstruction opc)
u8 dreg = opc & 0x1f;
dsp_op_read_reg(sreg, ECX);
#ifdef _M_IX86 // All32
MOVZX(32, 16, ECX, R(ECX));
#else
MOVZX(64, 16, ECX, R(ECX));
#endif
dmem_read();
dsp_op_write_reg(dreg, EAX);
dsp_conditional_extend_accum(dreg);
@ -167,11 +157,6 @@ void DSPEmitter::lrri(const UDSPInstruction opc)
u8 dreg = opc & 0x1f;
dsp_op_read_reg(sreg, ECX);
#ifdef _M_IX86 // All32
MOVZX(32, 16, ECX, R(ECX));
#else
MOVZX(64, 16, ECX, R(ECX));
#endif
dmem_read();
dsp_op_write_reg(dreg, EAX);
dsp_conditional_extend_accum(dreg);
@ -183,16 +168,17 @@ void DSPEmitter::lrri(const UDSPInstruction opc)
// Move value from data memory pointed by addressing register $S to register $D.
// Add indexing register $(0x4+S) to register $S.
// FIXME: Perform additional operation depending on destination register.
//void DSPEmitter::lrrn(const UDSPInstruction opc)
//{
// u8 sreg = (opc >> 5) & 0x3;
// u8 dreg = opc & 0x1f;
void DSPEmitter::lrrn(const UDSPInstruction opc)
{
u8 sreg = (opc >> 5) & 0x3;
u8 dreg = opc & 0x1f;
// u16 val = dsp_dmem_read(dsp_op_read_reg(sreg));
// dsp_op_write_reg(dreg, val);
// dsp_conditional_extend_accum(dreg);
// g_dsp.r[sreg] = dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
//}
dsp_op_read_reg(sreg, ECX);
dmem_read();
dsp_op_write_reg(dreg, EAX);
dsp_conditional_extend_accum(dreg);
increase_addr_reg(sreg);
}
// SRR @$D, $S
// 0001 1010 0dds ssss
@ -261,15 +247,21 @@ void DSPEmitter::srri(const UDSPInstruction opc)
// Store value from source register $S to a memory location pointed by
// addressing register $D. Add DSP_REG_IX0 register to register $D.
// FIXME: Perform additional operation depending on source register.
//void DSPEmitter::srrn(const UDSPInstruction opc)
//{
// u8 dreg = (opc >> 5) & 0x3;
// u8 sreg = opc & 0x1f;
void DSPEmitter::srrn(const UDSPInstruction opc)
{
u8 dreg = (opc >> 5) & 0x3;
u8 sreg = opc & 0x1f;
// u16 val = dsp_op_read_reg(sreg);
// dsp_dmem_write(g_dsp.r[dreg], val);
// g_dsp.r[dreg] = dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]);
//}
dsp_op_read_reg(sreg, ECX);
#ifdef _M_IX86 // All32
MOVZX(32, 16, EAX, M(&g_dsp.r[dreg]));
#else
MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, RAX, MDisp(R11,dreg*2));
#endif
dmem_write();
increase_addr_reg(dreg);
}
// ILRR $acD.m, @$arS
// 0000 001d 0001 00ss
@ -353,15 +345,25 @@ void DSPEmitter::ilrri(const UDSPInstruction opc)
// Move value from instruction memory pointed by addressing register
// $arS to mid accumulator register $acD.m. Add corresponding indexing
// register $ixS to addressing register $arS.
//void DSPEmitter::ilrrn(const UDSPInstruction opc)
//{
// u16 reg = opc & 0x3;
// u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
void DSPEmitter::ilrrn(const UDSPInstruction opc)
{
u16 reg = opc & 0x3;
u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
// g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
// dsp_conditional_extend_accum(dreg);
// g_dsp.r[reg] = dsp_increase_addr_reg(reg, (s16)g_dsp.r[DSP_REG_IX0 + reg]);
//}
#ifdef _M_IX86 // All32
MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
#else
MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOVZX(64, 16, RCX, MDisp(R11,reg*2));
#endif
imem_read();
#ifdef _M_IX86 // All32
MOV(16, M(&g_dsp.r[dreg]), R(EAX));
#else
MOV(64, R(R11), ImmPtr(&g_dsp.r));
MOV(16, MDisp(R11,dreg*2), R(RAX));
#endif
dsp_conditional_extend_accum(dreg);
increase_addr_reg(reg);
}
//} // namespace
//

8
Source/Core/DSPCore/Src/Jit/DSPJitUtil.cpp
View File

@ -420,10 +420,12 @@ void DSPEmitter::dmem_read()
CMP(16, R(ECX), Imm16(0x0fff));
FixupBranch dram = J_CC(CC_A);
// return g_dsp.dram[addr & DSP_DRAM_MASK];
AND(16, R(ECX), Imm16(DSP_DRAM_MASK));
#ifdef _M_X64
AND(16, R(ECX), Imm16(DSP_DRAM_MASK));
MOVZX(64, 16, RCX, R(RCX));
MOV(64, R(ESI), ImmPtr(g_dsp.dram));
#else
AND(32, R(ECX), Imm32(DSP_DRAM_MASK));
MOV(32, R(ESI), ImmPtr(g_dsp.dram));
#endif
MOV(16, R(EAX), MComplex(ESI, ECX, 2, 0));
@ -434,10 +436,12 @@ void DSPEmitter::dmem_read()
CMP(16, R(ECX), Imm16(0x1fff));
FixupBranch ifx = J_CC(CC_A);
// return g_dsp.coef[addr & DSP_COEF_MASK];
AND(16, R(ECX), Imm16(DSP_COEF_MASK));
#ifdef _M_X64
AND(16, R(ECX), Imm16(DSP_COEF_MASK));
MOVZX(64, 16, RCX, R(RCX));
MOV(64, R(ESI), ImmPtr(g_dsp.coef));
#else
AND(32, R(ECX), Imm32(DSP_COEF_MASK));
MOV(32, R(ESI), ImmPtr(g_dsp.coef));
#endif
MOV(16, R(EAX), MComplex(ESI,ECX,2,0));