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Merge pull request #995 from FioraAeterna/fma

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Add FMA support to emitter and use it in the JIT
This commit is contained in:
skidau
2014-10-12 13:56:18 +11:00
parent a373cc0654 9734f0c834
commit 9ddbdeb39f
6 changed files with 277 additions and 45 deletions
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66
Source/Core/Common/x64Emitter.h
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@ -294,8 +294,8 @@ private:
void WriteSSEOp(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes = 0);
void WriteSSSE3Op(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes = 0);
void WriteSSE41Op(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes = 0);
void WriteAVXOp(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes = 0);
void WriteAVXOp(u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
void WriteAVXOp(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int W = 0, int extrabytes = 0);
void WriteAVXOp(u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int W = 0, int extrabytes = 0);
void WriteVEXOp(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
void WriteBMI1Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
void WriteBMI2Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
@ -773,6 +773,68 @@ public:
void VUNPCKLPD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VUNPCKHPD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
// FMA
void VFMADD132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADD213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADD231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADD132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADD213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADD231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADD132SS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADD213SS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADD231SS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADD132SD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADD213SD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADD231SD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUB132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUB213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUB231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUB132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUB213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUB231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUB132SS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUB213SS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUB231SS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUB132SD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUB213SD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUB231SD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMADD132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMADD213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMADD231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMADD132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMADD213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMADD231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMADD132SS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMADD213SS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMADD231SS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMADD132SD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMADD213SD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMADD231SD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMSUB132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMSUB213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMSUB231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMSUB132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMSUB213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMSUB231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMSUB132SS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMSUB213SS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMSUB231SS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMSUB132SD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMSUB213SD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFNMSUB231SD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADDSUB132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADDSUB213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADDSUB231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADDSUB132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADDSUB213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMADDSUB231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUBADD132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUBADD213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUBADD231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUBADD132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUBADD213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
void VFMSUBADD231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg);
// VEX GPR instructions
void SARX(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2);
void SHLX(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2);