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Merge pull request #3716 from degasus/coretiming
CoreTiming: Drop ProcessFifoWaitEvents.
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commit
b16333a25c
@ -389,30 +389,6 @@ void ForceExceptionCheck(s64 cycles)
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}
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}
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// This raise only the events required while the fifo is processing data
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void ProcessFifoWaitEvents()
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{
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MoveEvents();
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if (!first)
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return;
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while (first)
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{
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if (first->time <= g_globalTimer)
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{
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Event* evt = first;
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first = first->next;
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event_types[evt->type].callback(evt->userdata, (int)(g_globalTimer - evt->time));
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FreeEvent(evt);
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}
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else
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{
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break;
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}
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}
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}
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void MoveEvents()
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{
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BaseEvent sevt;
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@ -480,14 +456,11 @@ void LogPendingEvents()
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void Idle()
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{
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// DEBUG_LOG(POWERPC, "Idle");
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if (SConfig::GetInstance().bSyncGPUOnSkipIdleHack)
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{
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// When the FIFO is processing data we must not advance because in this way
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// the VI will be desynchronized. So, We are waiting until the FIFO finish and
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// while we process only the events required by the FIFO.
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ProcessFifoWaitEvents();
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Fifo::FlushGpu();
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}
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@ -60,7 +60,6 @@ void RemoveEvent(int event_type);
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void RemoveAllEvents(int event_type);
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void Advance();
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void MoveEvents();
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void ProcessFifoWaitEvents();
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// Pretend that the main CPU has executed enough cycles to reach the next event.
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void Idle();
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@ -418,44 +418,9 @@ void CheckExceptions()
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}
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// EXTERNAL INTERRUPT
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else if (MSR & 0x0008000) // Handling is delayed until MSR.EE=1.
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else
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{
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if (exceptions & EXCEPTION_EXTERNAL_INT)
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{
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// Pokemon gets this "too early", it hasn't a handler yet
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SRR0 = NPC;
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SRR1 = MSR & 0x87C0FFFF;
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MSR |= (MSR >> 16) & 1;
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MSR &= ~0x04EF36;
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PC = NPC = 0x00000500;
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INFO_LOG(POWERPC, "EXCEPTION_EXTERNAL_INT");
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ppcState.Exceptions &= ~EXCEPTION_EXTERNAL_INT;
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_dbg_assert_msg_(POWERPC, (SRR1 & 0x02) != 0, "EXTERNAL_INT unrecoverable???");
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}
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else if (exceptions & EXCEPTION_PERFORMANCE_MONITOR)
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{
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SRR0 = NPC;
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SRR1 = MSR & 0x87C0FFFF;
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MSR |= (MSR >> 16) & 1;
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MSR &= ~0x04EF36;
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PC = NPC = 0x00000F00;
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INFO_LOG(POWERPC, "EXCEPTION_PERFORMANCE_MONITOR");
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ppcState.Exceptions &= ~EXCEPTION_PERFORMANCE_MONITOR;
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}
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else if (exceptions & EXCEPTION_DECREMENTER)
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{
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SRR0 = NPC;
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SRR1 = MSR & 0x87C0FFFF;
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MSR |= (MSR >> 16) & 1;
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MSR &= ~0x04EF36;
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PC = NPC = 0x00000900;
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INFO_LOG(POWERPC, "EXCEPTION_DECREMENTER");
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ppcState.Exceptions &= ~EXCEPTION_DECREMENTER;
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}
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CheckExternalExceptions();
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}
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}
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@ -276,7 +276,6 @@ void GatherPipeBursted()
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if (IsOnThread())
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SetCPStatusFromCPU();
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ProcessFifoEvents();
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// if we aren't linked, we don't care about gather pipe data
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if (!m_CPCtrlReg.GPLinkEnable)
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{
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@ -454,13 +453,6 @@ void SetCPStatusFromCPU()
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}
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}
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void ProcessFifoEvents()
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{
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if (IsOnThread() && (s_interrupt_waiting.load() || s_interrupt_finish_waiting.load() ||
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s_interrupt_token_waiting.load()))
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CoreTiming::ProcessFifoWaitEvents();
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}
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void Shutdown()
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{
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}
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@ -137,6 +137,5 @@ void SetInterruptFinishWaiting(bool waiting);
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void SetCpClearRegister();
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void SetCpControlRegister();
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void SetCpStatusRegister();
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void ProcessFifoEvents();
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} // namespace CommandProcessor
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