[ARM] rlwnmx implementation.

This commit is contained in:
Ryan Houdek 2013-09-16 11:52:25 +00:00
parent 43f2313ef9
commit b7f47bc2e1
3 changed files with 31 additions and 1 deletions

View File

@ -167,6 +167,7 @@ public:
void mulhwux(UGeckoInstruction _inst);
void rlwimix(UGeckoInstruction _inst);
void rlwinmx(UGeckoInstruction _inst);
void rlwnmx(UGeckoInstruction _inst);
void srawix(UGeckoInstruction _inst);
void extshx(UGeckoInstruction inst);
void extsbx(UGeckoInstruction inst);

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@ -775,6 +775,7 @@ void JitArm::rlwimix(UGeckoInstruction inst)
}
gpr.Unlock(rA, rB);
}
void JitArm::rlwinmx(UGeckoInstruction inst)
{
INSTRUCTION_START
@ -798,6 +799,34 @@ void JitArm::rlwinmx(UGeckoInstruction inst)
//m_GPR[inst.RA] = _rotl(m_GPR[inst.RS],inst.SH) & mask;
}
void JitArm::rlwnmx(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITIntegerOff)
u32 mask = Helper_Mask(inst.MB,inst.ME);
ARMReg RA = gpr.R(inst.RA);
ARMReg RS = gpr.R(inst.RS);
ARMReg RB = gpr.R(inst.RB);
ARMReg rA = gpr.GetReg();
ARMReg rB = gpr.GetReg();
MOVI2R(rA, mask);
// PPC rotates left, ARM rotates right. Swap it
MOV(rB, 32);
SUB(rB, rB, RB);
Operand2 Shift(RS, ST_ROR, rB); // Register shifted register
if (inst.Rc)
{
ANDS(RA, rA, Shift);
GenerateRC();
}
else
AND (RA, rA, Shift);
gpr.Unlock(rA, rB);
}
void JitArm::srawix(UGeckoInstruction inst)
{
INSTRUCTION_START

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@ -69,7 +69,7 @@ static GekkoOPTemplate primarytable[] =
{20, &JitArm::rlwimix}, //"rlwimix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_A | FL_IN_S | FL_RC_BIT}},
{21, &JitArm::rlwinmx}, //"rlwinmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
{23, &JitArm::Default}, //"rlwnmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_IN_B | FL_RC_BIT}},
{23, &JitArm::rlwnmx}, //"rlwnmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_IN_B | FL_RC_BIT}},
{24, &JitArm::arith}, //"ori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
{25, &JitArm::arith}, //"oris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},