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[AArch64] Support profiling by cycle counters if they are available to EL0

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This commit is contained in:
Ryan Houdek
2015-08-07 02:32:16 -05:00
parent 5110574c1f
commit b907576510
4 changed files with 73 additions and 8 deletions
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6
Source/Core/Common/Arm64Emitter.cpp
View File

@ -1102,6 +1102,12 @@ static void GetSystemReg(PStateField field, int &o0, int &op1, int &CRn, int &CR
case FIELD_FPSR:
o0 = 3; op1 = 3; CRn = 4; CRm = 4; op2 = 1;
break;
case FIELD_PMCR_EL0:
o0 = 3; op1 = 3; CRn = 9; CRm = 6; op2 = 0;
break;
case FIELD_PMCCNTR_EL0:
o0 = 3; op1 = 3; CRn = 9; CRm = 7; op2 = 0;
break;
default:
_assert_msg_(DYNA_REC, false, "Invalid PStateField to do a register move from/to");
break;

3
Source/Core/Common/Arm64Emitter.h
View File

@ -172,6 +172,8 @@ enum PStateField
FIELD_DAIFSet,
FIELD_DAIFClr,
FIELD_NZCV, // The only system registers accessible from EL0 (user space)
FIELD_PMCR_EL0,
FIELD_PMCCNTR_EL0,
FIELD_FPCR = 0x340,
FIELD_FPSR = 0x341,
};
@ -809,6 +811,7 @@ public:
void FCVTL(u8 size, ARM64Reg Rd, ARM64Reg Rn);
void FCVTL2(u8 size, ARM64Reg Rd, ARM64Reg Rn);
void FCVTN(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
void FCVTN2(u8 dest_size, ARM64Reg Rd, ARM64Reg Rn);
void FCVTZS(u8 size, ARM64Reg Rd, ARM64Reg Rn);
void FCVTZU(u8 size, ARM64Reg Rd, ARM64Reg Rn);
void FDIV(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);