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https://github.com/dolphin-emu/dolphin.git
synced 2025-07-23 06:09:50 -06:00
Remove Atomic.h
The STL has everything we need nowadays. I have tried to not alter any behavior or semantics with this change wherever possible. In particular, WriteLow and WriteHigh in CommandProcessor retain the ability to accidentally undo another thread's write to the upper half or lower half respectively. If that should be fixed, it should be done in a separate commit for clarity. One thing did change: The places where we were using += on a volatile variable (not an atomic operation) are now using fetch_add (actually an atomic operation). Tested with single core and dual core on x86-64 and AArch64.
This commit is contained in:
JosJuice
@ -1,16 +0,0 @@
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// Copyright 2008 Dolphin Emulator Project
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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#pragma once
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#ifdef _WIN32
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#include "Common/Atomic_Win32.h" // IWYU pragma: export
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#else
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// GCC-compatible compiler assumed!
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#include "Common/Atomic_GCC.h" // IWYU pragma: export
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#endif
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@ -1,86 +0,0 @@
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// Copyright 2009 Dolphin Emulator Project
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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// IWYU pragma: private, include "Common/Atomic.h"
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#pragma once
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#include "Common/Common.h"
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#include "Common/CommonTypes.h"
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// Atomic operations are performed in a single step by the CPU. It is
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// impossible for other threads to see the operation "half-done."
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//
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// Some atomic operations can be combined with different types of memory
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// barriers called "Acquire semantics" and "Release semantics", defined below.
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//
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// Acquire semantics: Future memory accesses cannot be relocated to before the
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// operation.
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//
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// Release semantics: Past memory accesses cannot be relocated to after the
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// operation.
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//
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// These barriers affect not only the compiler, but also the CPU.
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namespace Common
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{
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inline void AtomicAdd(volatile u32& target, u32 value)
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{
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__sync_add_and_fetch(&target, value);
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}
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inline void AtomicAnd(volatile u32& target, u32 value)
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{
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__sync_and_and_fetch(&target, value);
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}
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inline void AtomicDecrement(volatile u32& target)
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{
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__sync_add_and_fetch(&target, -1);
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}
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inline void AtomicIncrement(volatile u32& target)
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{
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__sync_add_and_fetch(&target, 1);
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}
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inline void AtomicOr(volatile u32& target, u32 value)
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{
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__sync_or_and_fetch(&target, value);
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}
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#ifndef __ATOMIC_RELAXED
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#error __ATOMIC_RELAXED not defined; your compiler version is too old.
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#endif
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template <typename T>
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inline T AtomicLoad(volatile T& src)
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{
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return __atomic_load_n(&src, __ATOMIC_RELAXED);
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}
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template <typename T>
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inline T AtomicLoadAcquire(volatile T& src)
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{
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return __atomic_load_n(&src, __ATOMIC_ACQUIRE);
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}
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template <typename T, typename U>
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inline void AtomicStore(volatile T& dest, U value)
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{
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__atomic_store_n(&dest, value, __ATOMIC_RELAXED);
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}
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template <typename T, typename U>
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inline void AtomicStoreRelease(volatile T& dest, U value)
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{
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__atomic_store_n(&dest, value, __ATOMIC_RELEASE);
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}
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template <typename T, typename U>
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inline T* AtomicExchangeAcquire(T* volatile& loc, U newval)
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{
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return __atomic_exchange_n(&loc, newval, __ATOMIC_ACQ_REL);
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}
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} // namespace Common
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@ -1,94 +0,0 @@
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// Copyright 2009 Dolphin Emulator Project
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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// IWYU pragma: private, include "Common/Atomic.h"
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#pragma once
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#include <Windows.h>
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#include <atomic>
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#include "Common/CommonTypes.h"
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// Atomic operations are performed in a single step by the CPU. It is
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// impossible for other threads to see the operation "half-done."
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//
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// Some atomic operations can be combined with different types of memory
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// barriers called "Acquire semantics" and "Release semantics", defined below.
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//
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// Acquire semantics: Future memory accesses cannot be relocated to before the
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// operation.
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//
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// Release semantics: Past memory accesses cannot be relocated to after the
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// operation.
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//
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// These barriers affect not only the compiler, but also the CPU.
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//
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// NOTE: Acquire and Release are not differentiated right now. They perform a
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// full memory barrier instead of a "one-way" memory barrier. The newest
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// Windows SDK has Acquire and Release versions of some Interlocked* functions.
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namespace Common
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{
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inline void AtomicAdd(volatile u32& target, u32 value)
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{
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_InterlockedExchangeAdd((volatile LONG*)&target, (LONG)value);
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}
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inline void AtomicAnd(volatile u32& target, u32 value)
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{
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_InterlockedAnd((volatile LONG*)&target, (LONG)value);
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}
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inline void AtomicIncrement(volatile u32& target)
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{
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_InterlockedIncrement((volatile LONG*)&target);
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}
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inline void AtomicDecrement(volatile u32& target)
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{
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_InterlockedDecrement((volatile LONG*)&target);
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}
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inline void AtomicOr(volatile u32& target, u32 value)
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{
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_InterlockedOr((volatile LONG*)&target, (LONG)value);
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}
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template <typename T>
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inline T AtomicLoad(volatile T& src)
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{
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return src; // 32-bit reads are always atomic.
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}
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template <typename T>
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inline T AtomicLoadAcquire(volatile T& src)
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{
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// 32-bit reads are always atomic.
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T result = src;
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// Compiler instruction only. x86 loads always have acquire semantics.
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std::atomic_thread_fence(std::memory_order_acquire);
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return result;
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}
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template <typename T, typename U>
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inline void AtomicStore(volatile T& dest, U value)
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{
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dest = (T)value; // 32-bit writes are always atomic.
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}
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template <typename T, typename U>
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inline void AtomicStoreRelease(volatile T& dest, U value)
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{
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// Compiler instruction only. x86 stores always have release semantics.
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std::atomic_thread_fence(std::memory_order_release);
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dest = (T)value; // 32-bit writes are always atomic.
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}
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template <typename T, typename U>
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inline T* AtomicExchangeAcquire(T* volatile& loc, U newval)
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{
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return (T*)_InterlockedExchangePointer_acq((void* volatile*)&loc, (void*)newval);
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}
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} // namespace Common
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@ -2,7 +2,6 @@ add_library(common
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Analytics.cpp
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Analytics.h
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Assert.h
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Atomic.h
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BitField.h
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BitSet.h
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BitUtils.h
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@ -221,10 +221,10 @@ public:
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template <typename T>
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void Do(std::atomic<T>& atomic)
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{
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T temp = atomic.load();
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T temp = atomic.load(std::memory_order_relaxed);
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Do(temp);
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if (mode == MODE_READ)
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atomic.store(temp);
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atomic.store(temp, std::memory_order_relaxed);
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}
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template <typename T>
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