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https://github.com/dolphin-emu/dolphin.git
synced 2025-07-24 14:49:42 -06:00
Common: Clean up brace placements
This commit is contained in:
@ -142,8 +142,9 @@ void OpArg::WriteRex(XEmitter *emit, int opBits, int bits, int customOp) const
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// Write REX if wr have REX bits to write, or if the operation accesses
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// SIL, DIL, BPL, or SPL.
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if (op != 0x40 ||
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(scale == SCALE_NONE && bits == 8 && (offsetOrBaseReg & 0x10c) == 4) ||
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(opBits == 8 && (customOp & 0x10c) == 4)) {
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(scale == SCALE_NONE && bits == 8 && (offsetOrBaseReg & 0x10c) == 4) ||
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(opBits == 8 && (customOp & 0x10c) == 4))
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{
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emit->Write8(op);
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// Check the operation doesn't access AH, BH, CH, or DH.
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_dbg_assert_(DYNA_REC, (offsetOrBaseReg & 0x100) == 0);
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@ -773,7 +774,8 @@ void XEmitter::BSR(int bits, X64Reg dest, OpArg src) {WriteBitSearchType(bits,de
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void XEmitter::MOVSX(int dbits, int sbits, X64Reg dest, OpArg src)
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{
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if (src.IsImm()) _assert_msg_(DYNA_REC, 0, "MOVSX - Imm argument");
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if (dbits == sbits) {
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if (dbits == sbits)
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{
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MOV(dbits, R(dest), src);
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return;
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}
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@ -804,7 +806,8 @@ void XEmitter::MOVSX(int dbits, int sbits, X64Reg dest, OpArg src)
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void XEmitter::MOVZX(int dbits, int sbits, X64Reg dest, OpArg src)
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{
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if (src.IsImm()) _assert_msg_(DYNA_REC, 0, "MOVZX - Imm argument");
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if (dbits == sbits) {
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if (dbits == sbits)
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{
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MOV(dbits, R(dest), src);
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return;
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}
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@ -1181,14 +1184,18 @@ void XEmitter::XCHG(int bits, const OpArg &a1, const OpArg &a2) {WriteNormalOp(t
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void XEmitter::IMUL(int bits, X64Reg regOp, OpArg a1, OpArg a2)
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{
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if (bits == 8) {
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if (bits == 8)
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{
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_assert_msg_(DYNA_REC, 0, "IMUL - illegal bit size!");
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return;
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}
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if (a1.IsImm()) {
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if (a1.IsImm())
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{
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_assert_msg_(DYNA_REC, 0, "IMUL - second arg cannot be imm!");
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return;
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}
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if (!a2.IsImm())
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{
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_assert_msg_(DYNA_REC, 0, "IMUL - third arg must be imm!");
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@ -1201,20 +1208,27 @@ void XEmitter::IMUL(int bits, X64Reg regOp, OpArg a1, OpArg a2)
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if (a2.GetImmBits() == 8 ||
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(a2.GetImmBits() == 16 && (s8)a2.offset == (s16)a2.offset) ||
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(a2.GetImmBits() == 32 && (s8)a2.offset == (s32)a2.offset)) {
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(a2.GetImmBits() == 32 && (s8)a2.offset == (s32)a2.offset))
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{
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Write8(0x6B);
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a1.WriteRest(this, 1, regOp);
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Write8((u8)a2.offset);
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} else {
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}
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else
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{
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Write8(0x69);
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if (a2.GetImmBits() == 16 && bits == 16) {
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if (a2.GetImmBits() == 16 && bits == 16)
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{
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a1.WriteRest(this, 2, regOp);
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Write16((u16)a2.offset);
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} else if (a2.GetImmBits() == 32 &&
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(bits == 32 || bits == 64)) {
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a1.WriteRest(this, 4, regOp);
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Write32((u32)a2.offset);
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} else {
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}
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else if (a2.GetImmBits() == 32 && (bits == 32 || bits == 64))
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{
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a1.WriteRest(this, 4, regOp);
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Write32((u32)a2.offset);
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}
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else
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{
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_assert_msg_(DYNA_REC, 0, "IMUL - unhandled case!");
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}
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}
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@ -1222,10 +1236,12 @@ void XEmitter::IMUL(int bits, X64Reg regOp, OpArg a1, OpArg a2)
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void XEmitter::IMUL(int bits, X64Reg regOp, OpArg a)
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{
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if (bits == 8) {
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if (bits == 8)
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{
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_assert_msg_(DYNA_REC, 0, "IMUL - illegal bit size!");
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return;
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}
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if (a.IsImm())
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{
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IMUL(bits, regOp, R(regOp), a) ;
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@ -1283,7 +1299,8 @@ void XEmitter::WriteAVXOp(int size, u16 sseOp, bool packed, X64Reg regOp1, X64Re
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void XEmitter::MOVD_xmm(X64Reg dest, const OpArg &arg) {WriteSSEOp(64, 0x6E, true, dest, arg, 0);}
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void XEmitter::MOVD_xmm(const OpArg &arg, X64Reg src) {WriteSSEOp(64, 0x7E, true, src, arg, 0);}
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void XEmitter::MOVQ_xmm(X64Reg dest, OpArg arg) {
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void XEmitter::MOVQ_xmm(X64Reg dest, OpArg arg)
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{
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// Alternate encoding
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// This does not display correctly in MSVC's debugger, it thinks it's a MOVD
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arg.operandReg = dest;
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@ -1294,7 +1311,8 @@ void XEmitter::MOVQ_xmm(X64Reg dest, OpArg arg) {
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arg.WriteRest(this, 0);
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}
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void XEmitter::MOVQ_xmm(OpArg arg, X64Reg src) {
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void XEmitter::MOVQ_xmm(OpArg arg, X64Reg src)
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{
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if (src > 7 || arg.IsSimpleReg())
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{
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// Alternate encoding
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@ -1305,7 +1323,9 @@ void XEmitter::MOVQ_xmm(OpArg arg, X64Reg src) {
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Write8(0x0f);
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Write8(0x7E);
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arg.WriteRest(this, 0);
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} else {
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}
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else
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{
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arg.operandReg = src;
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arg.WriteRex(this, 0, 0);
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Write8(0x66);
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@ -1466,42 +1486,50 @@ void XEmitter::PUNPCKLWD(X64Reg dest, const OpArg &arg) {WriteSSEOp(64, 0x61, tr
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void XEmitter::PUNPCKLDQ(X64Reg dest, const OpArg &arg) {WriteSSEOp(64, 0x62, true, dest, arg);}
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//void PUNPCKLQDQ(X64Reg dest, OpArg arg) {WriteSSEOp(64, 0x60, true, dest, arg);}
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void XEmitter::PSRLW(X64Reg reg, int shift) {
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void XEmitter::PSRLW(X64Reg reg, int shift)
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{
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WriteSSEOp(64, 0x71, true, (X64Reg)2, R(reg));
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Write8(shift);
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}
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void XEmitter::PSRLD(X64Reg reg, int shift) {
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void XEmitter::PSRLD(X64Reg reg, int shift)
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{
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WriteSSEOp(64, 0x72, true, (X64Reg)2, R(reg));
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Write8(shift);
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}
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void XEmitter::PSRLQ(X64Reg reg, int shift) {
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void XEmitter::PSRLQ(X64Reg reg, int shift)
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{
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WriteSSEOp(64, 0x73, true, (X64Reg)2, R(reg));
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Write8(shift);
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}
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void XEmitter::PSRLQ(X64Reg reg, OpArg arg) {
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void XEmitter::PSRLQ(X64Reg reg, OpArg arg)
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{
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WriteSSEOp(64, 0xd3, true, reg, arg);
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}
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void XEmitter::PSLLW(X64Reg reg, int shift) {
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void XEmitter::PSLLW(X64Reg reg, int shift)
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{
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WriteSSEOp(64, 0x71, true, (X64Reg)6, R(reg));
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Write8(shift);
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}
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void XEmitter::PSLLD(X64Reg reg, int shift) {
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void XEmitter::PSLLD(X64Reg reg, int shift)
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{
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WriteSSEOp(64, 0x72, true, (X64Reg)6, R(reg));
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Write8(shift);
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}
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void XEmitter::PSLLQ(X64Reg reg, int shift) {
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void XEmitter::PSLLQ(X64Reg reg, int shift)
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{
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WriteSSEOp(64, 0x73, true, (X64Reg)6, R(reg));
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Write8(shift);
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}
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// WARNING not REX compatible
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void XEmitter::PSRAW(X64Reg reg, int shift) {
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void XEmitter::PSRAW(X64Reg reg, int shift)
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{
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if (reg > 7)
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PanicAlert("The PSRAW-emitter does not support regs above 7");
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Write8(0x66);
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@ -1512,7 +1540,8 @@ void XEmitter::PSRAW(X64Reg reg, int shift) {
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}
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// WARNING not REX compatible
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void XEmitter::PSRAD(X64Reg reg, int shift) {
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void XEmitter::PSRAD(X64Reg reg, int shift)
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{
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if (reg > 7)
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PanicAlert("The PSRAD-emitter does not support regs above 7");
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Write8(0x66);
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@ -1632,11 +1661,14 @@ void XEmitter::FWAIT()
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void XEmitter::WriteFloatLoadStore(int bits, FloatOp op, OpArg arg)
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{
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int mf = 0;
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switch (bits) {
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case 32: mf = 0; break;
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case 64: mf = 2; break;
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default: _assert_msg_(DYNA_REC, 0, "WriteFloatLoadStore: bits is not 32 or 64");
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switch (bits)
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{
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case 32: mf = 0; break;
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case 64: mf = 2; break;
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default: _assert_msg_(DYNA_REC, 0, "WriteFloatLoadStore: bits is not 32 or 64");
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}
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Write8(0xd9 | (mf << 1));
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// x87 instructions use the reg field of the ModR/M byte as opcode:
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arg.WriteRest(this, 0, (X64Reg) op);
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@ -1727,20 +1759,23 @@ void XEmitter::CallCdeclFunction6(void* fnptr, u32 arg0, u32 arg1, u32 arg2, u32
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}
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// See header
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void XEmitter::___CallCdeclImport3(void* impptr, u32 arg0, u32 arg1, u32 arg2) {
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void XEmitter::___CallCdeclImport3(void* impptr, u32 arg0, u32 arg1, u32 arg2)
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{
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MOV(32, R(RCX), Imm32(arg0));
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MOV(32, R(RDX), Imm32(arg1));
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MOV(32, R(R8), Imm32(arg2));
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CALLptr(M(impptr));
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}
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void XEmitter::___CallCdeclImport4(void* impptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3) {
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void XEmitter::___CallCdeclImport4(void* impptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3)
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{
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MOV(32, R(RCX), Imm32(arg0));
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MOV(32, R(RDX), Imm32(arg1));
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MOV(32, R(R8), Imm32(arg2));
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MOV(32, R(R9), Imm32(arg3));
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CALLptr(M(impptr));
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}
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void XEmitter::___CallCdeclImport5(void* impptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4) {
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void XEmitter::___CallCdeclImport5(void* impptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4)
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{
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MOV(32, R(RCX), Imm32(arg0));
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MOV(32, R(RDX), Imm32(arg1));
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MOV(32, R(R8), Imm32(arg2));
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@ -1748,7 +1783,8 @@ void XEmitter::___CallCdeclImport5(void* impptr, u32 arg0, u32 arg1, u32 arg2, u
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MOV(32, MDisp(RSP, 0x20), Imm32(arg4));
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CALLptr(M(impptr));
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}
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void XEmitter::___CallCdeclImport6(void* impptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4, u32 arg5) {
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void XEmitter::___CallCdeclImport6(void* impptr, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 arg4, u32 arg5)
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{
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MOV(32, R(RCX), Imm32(arg0));
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MOV(32, R(RDX), Imm32(arg1));
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MOV(32, R(R8), Imm32(arg2));
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