From bf492c1ff3e2047e9c4525a8e93def75ef5da2f8 Mon Sep 17 00:00:00 2001
From: JosJuice <josjuice@gmail.com>
Date: Thu, 6 Oct 2022 23:04:44 +0200
Subject: [PATCH] JitArm64: Fix register number typo

I think this typo was actually ignored by the code, but nevertheless,
it should be fixed.
---
 Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
index 24c33b2d1c..1d0ce0a933 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
@@ -314,7 +314,7 @@ void JitArm64::GenerateFrsqrte()
   LSR(ARM64Reg::X2, ARM64Reg::X2, 48);
   AND(ARM64Reg::X2, ARM64Reg::X2, LogicalImm(0x10, 64));
   MOVP2R(ARM64Reg::X1, &Common::frsqrte_expected);
-  ORR(ARM64Reg::X2, ARM64Reg::X2, ARM64Reg::X3, ArithOption(ARM64Reg::X8, ShiftType::LSR, 48));
+  ORR(ARM64Reg::X2, ARM64Reg::X2, ARM64Reg::X3, ArithOption(ARM64Reg::X3, ShiftType::LSR, 48));
   EOR(ARM64Reg::X2, ARM64Reg::X2, LogicalImm(0x10, 64));
   ADD(ARM64Reg::X2, ARM64Reg::X1, ARM64Reg::X2, ArithOption(ARM64Reg::X2, ShiftType::LSL, 3));
   LDP(IndexType::Signed, ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::X2, 0);