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x64: add support for some x87 instructions
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@ -97,6 +97,12 @@ enum NormalOp {
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nrmXCHG,
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};
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enum FloatOp {
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floatLD = 0,
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floatST = 2,
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floatSTP = 3,
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};
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class XEmitter;
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// RIP addressing does not benefit from micro op fusion on Core arch
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@ -115,6 +121,7 @@ struct OpArg
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void WriteRex(XEmitter *emit, int opBits, int bits, int customOp = -1) const;
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void WriteVex(XEmitter* emit, int size, int packed, Gen::X64Reg regOp1, X64Reg regOp2) const;
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void WriteRest(XEmitter *emit, int extraBytes=0, X64Reg operandReg=(X64Reg)0xFF, bool warn_64bit_offset = true) const;
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void WriteFloatModRM(XEmitter *emit, FloatOp op);
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void WriteSingleByteOp(XEmitter *emit, u8 op, X64Reg operandReg, int bits);
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// This one is public - must be written to
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u64 offset; // use RIP-relative as much as possible - 64-bit immediates are not available.
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@ -244,6 +251,7 @@ private:
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void WriteSSEOp(int size, u8 sseOp, bool packed, X64Reg regOp, OpArg arg, int extrabytes = 0);
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void WriteAVXOp(int size, u8 sseOp, bool packed, X64Reg regOp, OpArg arg, int extrabytes = 0);
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void WriteAVXOp(int size, u8 sseOp, bool packed, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
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void WriteFloatLoadStore(int bits, FloatOp op, OpArg arg);
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void WriteNormalOp(XEmitter *emit, int bits, NormalOp op, const OpArg &a1, const OpArg &a2);
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protected:
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@ -424,6 +432,10 @@ public:
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void REP();
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void REPNE();
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// x87
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void FLD(int bits, OpArg src);
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void FST(int bits, OpArg dest);
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void FSTP(int bits, OpArg dest);
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void FWAIT();
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// SSE/SSE2: Floating point arithmetic
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