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DSPLLE - small fix
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@5221 8ced0084-cf51-0410-be5f-012b33b47a6e
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@ -177,96 +177,96 @@ const DSPOPCTemplate opcodes[] =
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// extended opcodes, note size of opcode will be set to 0
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//3 - main opcode defined by 9 bits, extension defined by last 7 bits!!
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{"XORR", 0x3000, 0xfc80, DSPInterpreter::xorr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true},
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{"ANDR", 0x3400, 0xfc80, DSPInterpreter::andr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true},
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{"ORR", 0x3800, 0xfc80, DSPInterpreter::orr, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true},
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{"ANDC", 0x3c00, 0xfe80, DSPInterpreter::andc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true},
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{"ORC", 0x3e00, 0xfe80, DSPInterpreter::orc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true},
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{"XORC", 0x3080, 0xfe80, DSPInterpreter::xorc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true},
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{"NOT", 0x3280, 0xfe80, DSPInterpreter::notc, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true},
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{"LSRNRX", 0x3480, 0xfc80, DSPInterpreter::lsrnrx, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true},
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{"ASRNRX", 0x3880, 0xfc80, DSPInterpreter::asrnrx, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true},
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{"LSRNR", 0x3c80, 0xfe80, DSPInterpreter::lsrnr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true},
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{"ASRNR", 0x3e80, 0xfe80, DSPInterpreter::asrnr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true},
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{"XORR", 0x3000, 0xfc80, DSPInterpreter::xorr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true},
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{"ANDR", 0x3400, 0xfc80, DSPInterpreter::andr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true},
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{"ORR", 0x3800, 0xfc80, DSPInterpreter::orr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true},
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{"ANDC", 0x3c00, 0xfe80, DSPInterpreter::andc, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true},
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{"ORC", 0x3e00, 0xfe80, DSPInterpreter::orc, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true},
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{"XORC", 0x3080, 0xfe80, DSPInterpreter::xorc, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true},
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{"NOT", 0x3280, 0xfe80, DSPInterpreter::notc, nop, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true},
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{"LSRNRX", 0x3480, 0xfc80, DSPInterpreter::lsrnrx, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true},
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{"ASRNRX", 0x3880, 0xfc80, DSPInterpreter::asrnrx, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true},
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{"LSRNR", 0x3c80, 0xfe80, DSPInterpreter::lsrnr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true},
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{"ASRNR", 0x3e80, 0xfe80, DSPInterpreter::asrnr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true},
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//4
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{"ADDR", 0x4000, 0xf800, DSPInterpreter::addr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true},
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{"ADDAX", 0x4800, 0xfc00, DSPInterpreter::addax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true},
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{"ADD", 0x4c00, 0xfe00, DSPInterpreter::add, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true},
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{"ADDP", 0x4e00, 0xfe00, DSPInterpreter::addp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"ADDR", 0x4000, 0xf800, DSPInterpreter::addr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true},
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{"ADDAX", 0x4800, 0xfc00, DSPInterpreter::addax, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true},
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{"ADD", 0x4c00, 0xfe00, DSPInterpreter::add, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true},
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{"ADDP", 0x4e00, 0xfe00, DSPInterpreter::addp, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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//5
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{"SUBR", 0x5000, 0xf800, DSPInterpreter::subr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true},
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{"SUBAX", 0x5800, 0xfc00, DSPInterpreter::subax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true},
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{"SUB", 0x5c00, 0xfe00, DSPInterpreter::sub, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true},
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{"SUBP", 0x5e00, 0xfe00, DSPInterpreter::subp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"SUBR", 0x5000, 0xf800, DSPInterpreter::subr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true},
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{"SUBAX", 0x5800, 0xfc00, DSPInterpreter::subax, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true},
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{"SUB", 0x5c00, 0xfe00, DSPInterpreter::sub, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true},
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{"SUBP", 0x5e00, 0xfe00, DSPInterpreter::subp, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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//6
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{"MOVR", 0x6000, 0xf800, DSPInterpreter::movr, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true},
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{"MOVAX", 0x6800, 0xfc00, DSPInterpreter::movax, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true},
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{"MOV", 0x6c00, 0xfe00, DSPInterpreter::mov, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true},
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{"MOVP", 0x6e00, 0xfe00, DSPInterpreter::movp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MOVR", 0x6000, 0xf800, DSPInterpreter::movr, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true},
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{"MOVAX", 0x6800, 0xfc00, DSPInterpreter::movax, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true},
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{"MOV", 0x6c00, 0xfe00, DSPInterpreter::mov, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true},
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{"MOVP", 0x6e00, 0xfe00, DSPInterpreter::movp, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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//7
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{"ADDAXL", 0x7000, 0xfc00, DSPInterpreter::addaxl, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true},
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{"INCM", 0x7400, 0xfe00, DSPInterpreter::incm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true},
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{"INC", 0x7600, 0xfe00, DSPInterpreter::inc, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"DECM", 0x7800, 0xfe00, DSPInterpreter::decm, nop, 1 | P_EXT, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true},
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{"DEC", 0x7a00, 0xfe00, DSPInterpreter::dec, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"NEG", 0x7c00, 0xfe00, DSPInterpreter::neg, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MOVNP", 0x7e00, 0xfe00, DSPInterpreter::movnp, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"ADDAXL", 0x7000, 0xfc00, DSPInterpreter::addaxl, nop, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true},
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{"INCM", 0x7400, 0xfe00, DSPInterpreter::incm, nop, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true},
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{"INC", 0x7600, 0xfe00, DSPInterpreter::inc, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"DECM", 0x7800, 0xfe00, DSPInterpreter::decm, nop, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true},
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{"DEC", 0x7a00, 0xfe00, DSPInterpreter::dec, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"NEG", 0x7c00, 0xfe00, DSPInterpreter::neg, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MOVNP", 0x7e00, 0xfe00, DSPInterpreter::movnp, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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//8
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{"NX", 0x8000, 0xf700, DSPInterpreter::nx, nop, 1 | P_EXT, 0, {}, true},
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{"CLR", 0x8100, 0xf700, DSPInterpreter::clr, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
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{"CMP", 0x8200, 0xff00, DSPInterpreter::cmp, nop, 1 | P_EXT, 0, {}, true},
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{"MULAXH", 0x8300, 0xff00, DSPInterpreter::mulaxh, nop, 1 | P_EXT, 0, {}, true},
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{"CLRP", 0x8400, 0xff00, DSPInterpreter::clrp, nop, 1 | P_EXT, 0, {}, true},
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{"TSTPROD", 0x8500, 0xff00, DSPInterpreter::tstprod, nop, 1 | P_EXT, 0, {}, true},
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{"TSTAXH", 0x8600, 0xfe00, DSPInterpreter::tstaxh, nop, 1 | P_EXT, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true},
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{"M2", 0x8a00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"M0", 0x8b00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"CLR15", 0x8c00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"SET15", 0x8d00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"SET16", 0x8e00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"SET40", 0x8f00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
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{"NX", 0x8000, 0xf700, DSPInterpreter::nx, nop, 1, 0, {}, true},
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{"CLR", 0x8100, 0xf700, DSPInterpreter::clr, nop, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
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{"CMP", 0x8200, 0xff00, DSPInterpreter::cmp, nop, 1, 0, {}, true},
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{"MULAXH", 0x8300, 0xff00, DSPInterpreter::mulaxh, nop, 1, 0, {}, true},
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{"CLRP", 0x8400, 0xff00, DSPInterpreter::clrp, nop, 1, 0, {}, true},
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{"TSTPROD", 0x8500, 0xff00, DSPInterpreter::tstprod, nop, 1, 0, {}, true},
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{"TSTAXH", 0x8600, 0xfe00, DSPInterpreter::tstaxh, nop, 1, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true},
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{"M2", 0x8a00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true},
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{"M0", 0x8b00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true},
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{"CLR15", 0x8c00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true},
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{"SET15", 0x8d00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true},
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{"SET16", 0x8e00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true},
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{"SET40", 0x8f00, 0xff00, DSPInterpreter::srbith, nop, 1, 0, {}, true},
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//9
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{"MUL", 0x9000, 0xf700, DSPInterpreter::mul, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true},
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{"ASR16", 0x9100, 0xf700, DSPInterpreter::asr16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
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{"MULMVZ", 0x9200, 0xf600, DSPInterpreter::mulmvz, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MULAC", 0x9400, 0xf600, DSPInterpreter::mulac, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MULMV", 0x9600, 0xf600, DSPInterpreter::mulmv, nop, 1 | P_EXT, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MUL", 0x9000, 0xf700, DSPInterpreter::mul, nop, 1, 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true},
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{"ASR16", 0x9100, 0xf700, DSPInterpreter::asr16, nop, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
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{"MULMVZ", 0x9200, 0xf600, DSPInterpreter::mulmvz, nop, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MULAC", 0x9400, 0xf600, DSPInterpreter::mulac, nop, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MULMV", 0x9600, 0xf600, DSPInterpreter::mulmv, nop, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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//a-b
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{"MULX", 0xa000, 0xe700, DSPInterpreter::mulx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true},
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{"ABS", 0xa100, 0xf700, DSPInterpreter::abs, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
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{"MULXMVZ", 0xa200, 0xe600, DSPInterpreter::mulxmvz, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MULXAC", 0xa400, 0xe600, DSPInterpreter::mulxac, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MULXMV", 0xa600, 0xe600, DSPInterpreter::mulxmv, nop, 1 | P_EXT, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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{"TST", 0xb100, 0xf700, DSPInterpreter::tst, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
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{"MULX", 0xa000, 0xe700, DSPInterpreter::mulx, nop, 1, 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true},
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{"ABS", 0xa100, 0xf700, DSPInterpreter::abs, nop, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
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{"MULXMVZ", 0xa200, 0xe600, DSPInterpreter::mulxmvz, nop, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MULXAC", 0xa400, 0xe600, DSPInterpreter::mulxac, nop, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MULXMV", 0xa600, 0xe600, DSPInterpreter::mulxmv, nop, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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{"TST", 0xb100, 0xf700, DSPInterpreter::tst, nop, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
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//c-d
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{"MULC", 0xc000, 0xe700, DSPInterpreter::mulc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true},
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{"CMPAR" , 0xc100, 0xe700, DSPInterpreter::cmpar, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true},
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{"MULCMVZ", 0xc200, 0xe600, DSPInterpreter::mulcmvz, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MULCAC", 0xc400, 0xe600, DSPInterpreter::mulcac, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MULCMV", 0xc600, 0xe600, DSPInterpreter::mulcmv, nop, 1 | P_EXT, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MULC", 0xc000, 0xe700, DSPInterpreter::mulc, nop, 1, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true},
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{"CMPAR" , 0xc100, 0xe700, DSPInterpreter::cmpar, nop, 1, 2, {{P_ACC, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true},
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{"MULCMVZ", 0xc200, 0xe600, DSPInterpreter::mulcmvz, nop, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MULCAC", 0xc400, 0xe600, DSPInterpreter::mulcac, nop, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MULCMV", 0xc600, 0xe600, DSPInterpreter::mulcmv, nop, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true},
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//e
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{"MADDX", 0xe000, 0xfc00, DSPInterpreter::maddx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true},
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{"MSUBX", 0xe400, 0xfc00, DSPInterpreter::msubx, nop, 1 | P_EXT, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true},
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{"MADDC", 0xe800, 0xfc00, DSPInterpreter::maddc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true},
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{"MSUBC", 0xec00, 0xfc00, DSPInterpreter::msubc, nop, 1 | P_EXT, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true},
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{"MADDX", 0xe000, 0xfc00, DSPInterpreter::maddx, nop, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true},
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{"MSUBX", 0xe400, 0xfc00, DSPInterpreter::msubx, nop, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true},
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{"MADDC", 0xe800, 0xfc00, DSPInterpreter::maddc, nop, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true},
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{"MSUBC", 0xec00, 0xfc00, DSPInterpreter::msubc, nop, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true},
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//f
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{"LSL16", 0xf000, 0xfe00, DSPInterpreter::lsl16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MADD", 0xf200, 0xfe00, DSPInterpreter::madd, nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true},
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{"LSR16", 0xf400, 0xfe00, DSPInterpreter::lsr16, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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{"MSUB", 0xf600, 0xfe00, DSPInterpreter::msub , nop, 1 | P_EXT, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true},
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{"ADDPAXZ", 0xf800, 0xfc00, DSPInterpreter::addpaxz, nop, 1 | P_EXT, 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_AX, 1, 0, 8, 0x0100}}, true}, //Think the args are wrong
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{"CLRL", 0xfc00, 0xfe00, DSPInterpreter::clrl, nop, 1 | P_EXT, 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true}, // clear acl0
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{"MOVPZ", 0xfe00, 0xfe00, DSPInterpreter::movpz, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
|
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{"LSL16", 0xf000, 0xfe00, DSPInterpreter::lsl16, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
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||||
{"MADD", 0xf200, 0xfe00, DSPInterpreter::madd, nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true},
|
||||
{"LSR16", 0xf400, 0xfe00, DSPInterpreter::lsr16, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
{"MSUB", 0xf600, 0xfe00, DSPInterpreter::msub , nop, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true},
|
||||
{"ADDPAXZ", 0xf800, 0xfc00, DSPInterpreter::addpaxz, nop, 1, 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_AX, 1, 0, 8, 0x0100}}, true}, //Think the args are wrong
|
||||
{"CLRL", 0xfc00, 0xfe00, DSPInterpreter::clrl, nop, 1, 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true}, // clear acl0
|
||||
{"MOVPZ", 0xfe00, 0xfe00, DSPInterpreter::movpz, nop, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true},
|
||||
};
|
||||
|
||||
const DSPOPCTemplate cw =
|
||||
|
Reference in New Issue
Block a user