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x64Emitter: Support FLD/FSTP with 80 bits operands
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@ -1660,25 +1660,27 @@ void XEmitter::FWAIT()
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}
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// TODO: make this more generic
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void XEmitter::WriteFloatLoadStore(int bits, FloatOp op, OpArg arg)
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void XEmitter::WriteFloatLoadStore(int bits, FloatOp op, FloatOp op_80b, OpArg arg)
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{
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int mf = 0;
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_assert_msg_(DYNA_REC, !(bits == 80 && op_80b == floatINVALID), "WriteFloatLoadStore: 80 bits not supported for this instruction");
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switch (bits)
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{
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case 32: mf = 0; break;
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case 64: mf = 2; break;
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default: _assert_msg_(DYNA_REC, 0, "WriteFloatLoadStore: bits is not 32 or 64");
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case 64: mf = 4; break;
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case 80: mf = 2; break;
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default: _assert_msg_(DYNA_REC, 0, "WriteFloatLoadStore: invalid bits (should be 32/64/80)");
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}
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Write8(0xd9 | (mf << 1));
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Write8(0xd9 | mf);
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// x87 instructions use the reg field of the ModR/M byte as opcode:
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if (bits == 80)
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op = op_80b;
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arg.WriteRest(this, 0, (X64Reg) op);
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}
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void XEmitter::FLD(int bits, OpArg src) {WriteFloatLoadStore(bits, floatLD, src);}
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void XEmitter::FST(int bits, OpArg dest) {WriteFloatLoadStore(bits, floatST, dest);}
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void XEmitter::FSTP(int bits, OpArg dest) {WriteFloatLoadStore(bits, floatSTP, dest);}
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void XEmitter::FLD(int bits, OpArg src) {WriteFloatLoadStore(bits, floatLD, floatLD80, src);}
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void XEmitter::FST(int bits, OpArg dest) {WriteFloatLoadStore(bits, floatST, floatINVALID, dest);}
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void XEmitter::FSTP(int bits, OpArg dest) {WriteFloatLoadStore(bits, floatSTP, floatSTP80, dest);}
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void XEmitter::FNSTSW_AX() { Write8(0xDF); Write8(0xE0); }
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void XEmitter::RDTSC() { Write8(0x0F); Write8(0x31); }
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