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docs/DSP: Rename CMPAR to CMPAXH

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Pokechu22 2022-05-22 16:47:08 -07:00
parent 8d880cd86e
commit ce4aba7d5e
1 changed files with 6 additions and 5 deletions
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docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex
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@ -46,7 +46,7 @@
% Document front page material % Document front page material
\title{\textbf{\Huge GameCube DSP User's Manual}} \title{\textbf{\Huge GameCube DSP User's Manual}}
\author{Reverse-engineered and documented by Duddie \\ \href{mailto:duddie@walla.com}{duddie@walla.com}} \author{Reverse-engineered and documented by Duddie \\ \href{mailto:duddie@walla.com}{duddie@walla.com}}
\date{\today\\v0.1.2} \date{\today\\v0.1.3}
% Title formatting commands % Title formatting commands
\newcommand{\OpcodeTitle}[1]{\subsection{#1}\label{instruction:#1}} \newcommand{\OpcodeTitle}[1]{\subsection{#1}\label{instruction:#1}}
@ -260,6 +260,7 @@ The purpose of this documentation is purely academic and it aims at understandin
0.1.0 & 2021.08.21 & Pokechu22 & Added missing instructions, improved documentation of hardware registers, documented additional behaviors, and improved formatting. \\ \hline 0.1.0 & 2021.08.21 & Pokechu22 & Added missing instructions, improved documentation of hardware registers, documented additional behaviors, and improved formatting. \\ \hline
0.1.1 & 2022.05.14 & xperia64 & Added tested DSP bootloading transfer size \\ \hline 0.1.1 & 2022.05.14 & xperia64 & Added tested DSP bootloading transfer size \\ \hline
0.1.2 & 2022.05.21 & Pokechu22 & Fixed ``ILLR'' typo in Instruction Memory section \\ \hline 0.1.2 & 2022.05.21 & Pokechu22 & Fixed ``ILLR'' typo in Instruction Memory section \\ \hline
0.1.3 & 2022.05.27 & Pokechu22 & Renamed \texttt{CMPAR} instruction to \texttt{CMPAXH} \\ \hline
\end{tabular} \end{tabular}
\end{table} \end{table}
@ -1929,17 +1930,17 @@ A ``-'' indicates that the flag retains its previous value, a ``0'' indicates th
\DSPOpcodeFlags{X}{-}{X}{X}{X}{X}{X}{X} \DSPOpcodeFlags{X}{-}{X}{X}{X}{X}{X}{X}
\end{DSPOpcode} \end{DSPOpcode}
\begin{DSPOpcode}{CMPAR} \begin{DSPOpcode}{CMPAXH}
\begin{DSPOpcodeBytefield}{16} \begin{DSPOpcodeBytefield}{16}
\monobitbox{4}{110r} & \monobitbox{4}{s001} & \monobitbox{4}{xxxx} & \monobitbox{4}{xxxx} \monobitbox{4}{110r} & \monobitbox{4}{s001} & \monobitbox{4}{xxxx} & \monobitbox{4}{xxxx}
\end{DSPOpcodeBytefield} \end{DSPOpcodeBytefield}
\begin{DSPOpcodeFormat} \begin{DSPOpcodeFormat}
CMPAR $acS $axR.h CMPAXH $acS, $axR.h
\end{DSPOpcodeFormat} \end{DSPOpcodeFormat}
\begin{DSPOpcodeDescription} \begin{DSPOpcodeDescription}
\item Compares accumulator \Register{\$acS} with accumulator \Register{\$axR.h}. \item Compares accumulator \Register{\$acS} with high part of secondary accumulator \Register{\$axR.h}.
\end{DSPOpcodeDescription} \end{DSPOpcodeDescription}
\begin{DSPOpcodeOperation} \begin{DSPOpcodeOperation}
@ -5065,7 +5066,7 @@ Instruction & Opcode & Page \\ \hline
\OpcodeRow{101s t11r xxxx xxxx}{MULXMV} \OpcodeRow{101s t11r xxxx xxxx}{MULXMV}
\OpcodeRowSkip \OpcodeRowSkip
\OpcodeRow{110s t000 xxxx xxxx}{MULC} \OpcodeRow{110s t000 xxxx xxxx}{MULC}
\OpcodeRow{110r s001 xxxx xxxx}{CMPAR} \OpcodeRow{110r s001 xxxx xxxx}{CMPAXH}
\OpcodeRow{110s t01r xxxx xxxx}{MULCMVZ} \OpcodeRow{110s t01r xxxx xxxx}{MULCMVZ}
\OpcodeRow{110s t10r xxxx xxxx}{MULCAC} \OpcodeRow{110s t10r xxxx xxxx}{MULCAC}
\OpcodeRow{110s t11r xxxx xxxx}{MULCMV} \OpcodeRow{110s t11r xxxx xxxx}{MULCMV}