From d0de68c41bb7d1676ae99cf750cb1bbabb7317a1 Mon Sep 17 00:00:00 2001 From: Bram Speeckaert Date: Tue, 1 Nov 2022 12:21:24 +0100 Subject: [PATCH] JitArm64: cmp - Optimize general case We can merge an SXTW with the SUB, eliminating one instruction. In addition, it is no longer necessary to allocate a temporary register, reducing register pressure. Before: 0x93407f59 sxtw x25, w26 0x93407ebb sxtw x27, w21 0xcb1b033b sub x27, x25, x27 After: 0x93407f5b sxtw x27, w26 0xcb35c37b sub x27, x27, w21, sxtw --- Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp index 6378c322e7..f315efb976 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp @@ -595,16 +595,11 @@ void JitArm64::cmp(UGeckoInstruction inst) } else { - ARM64Reg WA = gpr.GetReg(); - ARM64Reg XA = EncodeRegTo64(WA); ARM64Reg RA = gpr.R(a); ARM64Reg RB = gpr.R(b); - SXTW(XA, RA); - SXTW(CR, RB); - SUB(CR, XA, CR); - - gpr.Unlock(WA); + SXTW(CR, RA); + SUB(CR, CR, RB, ArithOption(RB, ExtendSpecifier::SXTW)); } }