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git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2921 8ced0084-cf51-0410-be5f-012b33b47a6e
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omegadox
@ -57,6 +57,22 @@ void BPWritten(const Bypass& bp)
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// had to be ditched and the games seem to work fine with out it.
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// --------------------------------------------------------------------------------------------------------
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// Debugging only, this lets you skip a bp update
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//static int times = 0;
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//static bool enable = false;
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//switch (bp.address)
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//{
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//case BPMEM_CONSTANTALPHA:
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// {
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// if (times == 0 && enable)
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// return;
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// else
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// break;
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// }
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//default: break;
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//}
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FlushPipeline();
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((u32*)&bpmem)[bp.address] = bp.newvalue;
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@ -152,7 +168,7 @@ void BPWritten(const Bypass& bp)
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break;
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default:
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DEBUG_LOG(VIDEO, "GXSetDrawDone ??? (value 0x%02X)", (bp.newvalue & 0xFFFF));
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WARN_LOG(VIDEO, "GXSetDrawDone ??? (value 0x%02X)", (bp.newvalue & 0xFFFF));
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break;
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}
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break;
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@ -260,12 +276,12 @@ void BPWritten(const Bypass& bp)
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case BPMEM_FOGCOLOR: // Fog Color
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PixelShaderManager::SetFogColorChanged();
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break;
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case BPMEM_ALPHACOMPARE:
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case BPMEM_ALPHACOMPARE: // Compare Alpha Values
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PRIM_LOG("alphacmp: ref0=%d, ref1=%d, comp0=%d, comp1=%d, logic=%d", bpmem.alphaFunc.ref0,
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bpmem.alphaFunc.ref1, bpmem.alphaFunc.comp0, bpmem.alphaFunc.comp1, bpmem.alphaFunc.logic);
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PixelShaderManager::SetAlpha(bpmem.alphaFunc);
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break;
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case BPMEM_ZTEX1: // BIAS
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case BPMEM_BIAS: // BIAS
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PRIM_LOG("ztex bias=0x%x", bpmem.ztex1.bias);
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PixelShaderManager::SetZTextureBias(bpmem.ztex1.bias);
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break;
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@ -291,28 +307,50 @@ void BPWritten(const Bypass& bp)
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case BPMEM_FIELDMODE:
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SetInterlacingMode(bp);
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break;
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case BPMEM_CLOCK0: // Debugging/Profiling info, we don't care about them
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case BPMEM_CLOCK1:
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case BPMEM_SU_COUNTER:
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case BPMEM_RAS_COUNTER:
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case BPMEM_SETGPMETRIC:
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// ---------------------------------------------------
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// Debugging/Profiling info, we don't care about them
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// ---------------------------------------------------
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case BPMEM_CLOCK0: // Some Clock
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case BPMEM_CLOCK1: // Some Clock
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case BPMEM_SU_COUNTER: // Pixel or Poly Count
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case BPMEM_RAS_COUNTER: // Sound Count of something in the Texture Units
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case BPMEM_SETGPMETRIC: // Set the Graphic Proccessor Metric
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break;
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// ----------------
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// EFB Copy config
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// ----------------
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case BPMEM_EFB_TL: // EFB Source Rect. Top, Left
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case BPMEM_EFB_BR: // EFB Source Rect. Bottom, Right (w, h - 1)
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case BPMEM_EFB_ADDR: // EFB Target Address
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break;
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case BPMEM_CLEAR_AR: // Set Clear Alpha and Red Components
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case BPMEM_CLEAR_GB: // Green and Blue
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case BPMEM_CLEAR_Z: // Clear Z, 24-bit Z Value
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// --------------
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// Clear Config
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// --------------
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case BPMEM_CLEAR_AR: // Alpha and Red Components
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case BPMEM_CLEAR_GB: // Green and Blue Components
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case BPMEM_CLEAR_Z: // Z Components (24-bit Zbuffer)
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break;
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case BPMEM_CLEARBBOX1: // let's hope not many games use bboxes..
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case BPMEM_CLEARBBOX2: // TODO(ector): add something that watches bboxes
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// -------------------------
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// Culling Occulsion, we don't support this
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// let's hope not many games use bboxes..
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// TODO(ector): add something that watches bboxes
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// -------------------------
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case BPMEM_CLEARBBOX1:
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case BPMEM_CLEARBBOX2:
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break;
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case BPMEM_PE_CONTROL: // Pixel Engine Control (GXSetZCompLoc, GXPixModeSync)
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case BPMEM_ZCOMPARE: // Set the Z-Compare
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case BPMEM_TEXINVALIDATE: // Used, if game has manual control the Texture Cache, which we don't allow
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case BPMEM_MIPMAP_STRIDE: // MipMap Stride Channel
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case BPMEM_COPYYSCALE: // Display Copy Y Scale
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case BPMEM_IREF: // Something to do with Tev ordering
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case BPMEM_IREF: /* 24 RID
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21 BC3 - Ind. Tex Stage 3 NTexCoord
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18 BI3 - Ind. Tex Stage 3 NTexMap
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15 BC2 - Ind. Tex Stage 2 NTexCoord
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12 BI2 - Ind. Tex Stage 2 NTexMap
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9 BC1 - Ind. Tex Stage 1 NTexCoord
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6 BI1 - Ind. Tex Stage 1 NTexMap
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3 BC0 - Ind. Tex Stage 0 NTexCoord
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0 BI0 - Ind. Tex Stage 0 NTexMap */
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break;
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case BPMEM_TEV_KSEL: // Texture Environment Swap Mode Table 0
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case BPMEM_TEV_KSEL+1:// Texture Environment Swap Mode Table 1
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@ -323,10 +361,13 @@ void BPWritten(const Bypass& bp)
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case BPMEM_TEV_KSEL+6:// Texture Environment Swap Mode Table 6
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case BPMEM_TEV_KSEL+7:// Texture Environment Swap Mode Table 7
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break;
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case BPMEM_BP_MASK: // Masks
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case BPMEM_IND_IMASK:
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case BPMEM_BP_MASK: // This Register can be used to limit to which bits of BP registers is actually written to. the mask is
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// only valid for the next BP command, and will reset itself.
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case BPMEM_IND_IMASK: // Index Mask ?
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break;
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case BPMEM_UNKNOWN: // This is always set to 0xF at boot of any game, so this sounds like a useless reg
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if (bp.newvalue != 0x0F)
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PanicAlert("Unknown is not 0xF! val = 0x%08x", bp.newvalue);
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break;
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// ------------------------------------------------
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@ -348,11 +389,11 @@ void BPWritten(const Bypass& bp)
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case BPMEM_TREF+6:
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case BPMEM_TREF+7:
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break;
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// ---------------------------------------------
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// Mipmapping control of the polygon's wrapping
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// ---------------------------------------------
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case BPMEM_SU_SSIZE: // U
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case BPMEM_SU_TSIZE: // V
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// ----------------------
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// Set a triangle's Wrap
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// ----------------------
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case BPMEM_SU_SSIZE:
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case BPMEM_SU_TSIZE:
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case BPMEM_SU_SSIZE+2:
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case BPMEM_SU_TSIZE+2:
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case BPMEM_SU_SSIZE+4:
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@ -369,12 +410,13 @@ void BPWritten(const Bypass& bp)
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case BPMEM_SU_TSIZE+14:
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break;
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// ------------------------
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// Mipmapping mode control
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// BPMEM_TX_SETMODE0 - (Texture lookup and filtering mode) LOD/BIAS Clamp, MaxAnsio, LODBIAS, DiagLoad, Min Filter, Mag Filter, Wrap T, S
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// BPMEM_TX_SETMODE1 - (LOD Stuff) - Max LOD, Min LOD
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// ------------------------
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case BPMEM_TX_SETMODE0: // 0x90 for Linear, Index 0
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case BPMEM_TX_SETMODE0: // (0x90 for linear)
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case BPMEM_TX_SETMODE0+1:
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case BPMEM_TX_SETMODE0+2:
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case BPMEM_TX_SETMODE0+3: // Index 4
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case BPMEM_TX_SETMODE0+3:
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case BPMEM_TX_SETMODE1:
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case BPMEM_TX_SETMODE1+1:
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case BPMEM_TX_SETMODE1+2:
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@ -390,7 +432,10 @@ void BPWritten(const Bypass& bp)
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SetSamplerState(bp);
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break;
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// --------------------------------------------
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// Mipmapping control of the polygon's texture
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// BPMEM_TX_SETIMAGE0 - Texture width, height, format
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// BPMEM_TX_SETIMAGE1 - even LOD address in TMEM - Image Type, Cache Height, Cache Width, TMEM Offset
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// BPMEM_TX_SETIMAGE2 - odd LOD address in TMEM - Cache Height, Cache Width, TMEM Offset
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// BPMEM_TX_SETIMAGE3 - Address of Texture in main memory
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// --------------------------------------------
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case BPMEM_TX_SETIMAGE0:
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case BPMEM_TX_SETIMAGE0+1:
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@ -426,7 +471,8 @@ void BPWritten(const Bypass& bp)
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case BPMEM_TX_SETIMAGE3_4+3:
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break;
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// -------------------------------
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// Mipmapping control of the TLUT
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// Set a TLUT
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// BPMEM_TX_SETTLUT - Format, TMEM Offset (offset of TLUT from start of TMEM high bank > > 5)
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// -------------------------------
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case BPMEM_TX_SETTLUT:
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case BPMEM_TX_SETTLUT+1:
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@ -487,6 +533,8 @@ void BPWritten(const Bypass& bp)
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break;
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// --------------------------------------------------
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// Set Color/Alpha of a Tev
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// BPMEM_TEV_COLOR_ENV - Dest, Shift, Clamp, Sub, Bias, Sel A, Sel B, Sel C, Sel D
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// BPMEM_TEV_ALPHA_ENV - Dest, Shift, Clamp, Sub, Bias, Sel A, Sel B, Sel C, Sel D, T Swap, R Swap
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// --------------------------------------------------
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case BPMEM_TEV_COLOR_ENV: // Texture Environment 1
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case BPMEM_TEV_ALPHA_ENV:
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