piwalker/dolphin
1
0
Fork 0
mirror of https://github.com/dolphin-emu/dolphin.git synced 2025-07-12 08:49:36 -06:00
Code Issues Packages Projects Releases Wiki Activity

Fix updating the register even if an exception occurred in MMU mode.

Browse Source
This commit is contained in:
comex
2013-10-07 02:32:50 -04:00
parent a9908fdf09
commit d6f0ecebb4
1 changed files with 18 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
Source/Core/Core/Src/PowerPC/Jit64/Jit_LoadStore.cpp
View File

@ -150,6 +150,8 @@ void Jit64::lXXx(UGeckoInstruction inst)
else else
update = ((inst.OPCD & 1) != 0); update = ((inst.OPCD & 1) != 0);
bool zeroOffset = inst.OPCD != 31 && inst.SIMM_16 == 0;
// Prepare address operand // Prepare address operand
Gen::OpArg opAddress; Gen::OpArg opAddress;
if (!update && !a) if (!update && !a)
@ -170,23 +172,23 @@ void Jit64::lXXx(UGeckoInstruction inst)
} }
else else
{ {
if ((inst.OPCD != 31) && gpr.R(a).IsImm()) if ((inst.OPCD != 31) && gpr.R(a).IsImm() && !js.memcheck)
{ {
u32 val = (u32)gpr.R(a).offset + (s32)inst.SIMM_16; u32 val = (u32)gpr.R(a).offset + (s32)inst.SIMM_16;
opAddress = Imm32(val); opAddress = Imm32(val);
if (update) if (update && !js.memcheck)
gpr.SetImmediate32(a, val); gpr.SetImmediate32(a, val);
} }
else if ((inst.OPCD == 31) && gpr.R(a).IsImm() && gpr.R(b).IsImm()) else if ((inst.OPCD == 31) && gpr.R(a).IsImm() && gpr.R(b).IsImm() && !js.memcheck)
{ {
u32 val = (u32)gpr.R(a).offset + (u32)gpr.R(b).offset; u32 val = (u32)gpr.R(a).offset + (u32)gpr.R(b).offset;
opAddress = Imm32(val); opAddress = Imm32(val);
if (update) if (update && !js.memcheck)
gpr.SetImmediate32(a, val); gpr.SetImmediate32(a, val);
} }
else else
{ {
if (update || (inst.OPCD != 31 && inst.SIMM_16 == 0)) if ((update && !js.memcheck) || zeroOffset)
{ {
gpr.BindToRegister(a, true, update); gpr.BindToRegister(a, true, update);
opAddress = gpr.R(a); opAddress = gpr.R(a);
@ -200,7 +202,7 @@ void Jit64::lXXx(UGeckoInstruction inst)
if (inst.OPCD == 31) if (inst.OPCD == 31)
ADD(32, opAddress, gpr.R(b)); ADD(32, opAddress, gpr.R(b));
else else if (inst.SIMM_16 != 0)
ADD(32, opAddress, Imm32((u32)(s32)inst.SIMM_16)); ADD(32, opAddress, Imm32((u32)(s32)inst.SIMM_16));
} }
} }
@ -209,6 +211,14 @@ void Jit64::lXXx(UGeckoInstruction inst)
gpr.BindToRegister(d, false, true); gpr.BindToRegister(d, false, true);
SafeLoadToReg(gpr.RX(d), opAddress, accessSize, 0, RegistersInUse(), signExtend); SafeLoadToReg(gpr.RX(d), opAddress, accessSize, 0, RegistersInUse(), signExtend);
if (update && js.memcheck && !zeroOffset)
{
gpr.BindToRegister(a, false, true);
MEMCHECK_START
MOV(32, gpr.R(a), opAddress);
MEMCHECK_END
}
gpr.UnlockAll(); gpr.UnlockAll();
gpr.UnlockAllX(); gpr.UnlockAllX();
} }