piwalker/dolphin
1
0
Fork 0
mirror of https://github.com/dolphin-emu/dolphin.git synced 2025-07-21 13:20:27 -06:00
Code Issues Packages Projects Releases Wiki Activity

Don't set DAZ on x86 in non-IEEE mode.

Browse Source 
I have no idea why we were using it in the first place; it doesn't match
the behavior of PPC NI flag.
This commit is contained in:
magumagu
2014-06-14 21:22:34 -07:00
parent d7736ac714
commit d905cbfd5d
4 changed files with 4 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
Source/Core/Common/x64CPUDetect.cpp
View File

@ -162,32 +162,10 @@ void CPUInfo::Detect()
if ((cpu_id[2] >> 22) & 1) bMOVBE = true;
if ((cpu_id[2] >> 25) & 1) bAES = true;
// To check DAZ support, we first need to check FXSAVE support.
if ((cpu_id[3] >> 24) & 1)
{
// We can use FXSAVE.
bFXSR = true;
GC_ALIGNED16(u8 fx_state[512]);
memset(fx_state, 0, sizeof(fx_state));
#ifdef _WIN32
#if _M_X86_32
_fxsave(fx_state);
#elif _M_X86_64
_fxsave64(fx_state);
#endif
#else
__asm__("fxsave %0" : "=m" (fx_state));
#endif
// lowest byte of MXCSR_MASK
if ((fx_state[0x1C] >> 6) & 1)
{
// On x86, the FTZ field (supported since SSE1) only flushes denormal _outputs_ to zero,
// now that we checked DAZ support (flushing denormal _inputs_ to zero),
// we can set our generic flag.
bFlushToZero = true;
}
}
// AVX support requires 3 separate checks:
@ -204,6 +182,9 @@ void CPUInfo::Detect()
}
}
}
bFlushToZero = bSSE;
if (max_ex_fn >= 0x80000004) {
// Extract brand string
__cpuid(cpu_id, 0x80000002);
@ -269,7 +250,3 @@ std::string CPUInfo::Summarize()
return sum;
}
bool CPUInfo::IsUnsafe()
{
return !bFlushToZero;
}