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Document some UGeckoInstruction fields
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Tillmann Karras
parent
f605ea9eeb
commit
e4a81f32d4
@ -23,17 +23,25 @@ union UGeckoInstruction
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struct
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{
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// Record bit
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// 1, if the condition register should be updated by this instruction
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u32 Rc : 1;
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u32 SUBOP10 : 10;
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// Source GPR
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u32 RB : 5;
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// Source or destination GPR
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u32 RA : 5;
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// Destination GPR
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u32 RD : 5;
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// Primary opcode
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u32 OPCD : 6;
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}; // changed
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};
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struct
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{
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// Immediate, signed 16-bit
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signed SIMM_16 : 16;
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u32 : 5;
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// Conditions on which to trap
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u32 TO : 5;
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u32 OPCD_2 : 6;
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};
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@ -43,11 +51,13 @@ union UGeckoInstruction
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u32 : 10;
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u32 : 5;
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u32 : 5;
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// Source GPR
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u32 RS : 5;
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u32 OPCD_3 : 6;
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};
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struct
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{
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// Immediate, unsigned 16-bit
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u32 UIMM : 16;
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u32 : 5;
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u32 : 5;
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@ -55,8 +65,13 @@ union UGeckoInstruction
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};
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struct
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{
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// Link bit
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// 1, if branch instructions should put the address of the next instruction into the link register
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u32 LK : 1;
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// Absolute address bit
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// 1, if the immediate field represents an absolute address
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u32 AA : 1;
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// Immediate, signed 24-bit
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u32 LI : 24;
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u32 OPCD_5 : 6;
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};
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@ -64,8 +79,11 @@ union UGeckoInstruction
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{
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u32 LK_2 : 1;
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u32 AA_2 : 1;
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// Branch displacement, signed 14-bit (right-extended by 0b00)
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u32 BD : 14;
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// Branch condition
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u32 BI : 5;
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// Conditional branch control
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u32 BO : 5;
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u32 OPCD_6 : 6;
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};
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@ -83,8 +101,10 @@ union UGeckoInstruction
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u32 : 11;
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u32 RB_2 : 5;
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u32 RA_2 : 5;
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// ?
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u32 L : 1;
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u32 : 1;
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// Destination field in CR or FPSCR
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u32 CRFD : 3;
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u32 OPCD_8 : 6;
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};
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@ -102,7 +122,7 @@ union UGeckoInstruction
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u32 UIMM_2 : 16;
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u32 RA_4 : 5;
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u32 L_3 : 1;
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u32 dummy2 : 1;
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u32 : 1;
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u32 CRFD_3 : 3;
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u32 OPCD_A : 6;
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};
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@ -113,13 +133,14 @@ union UGeckoInstruction
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u32 RB_5 : 5;
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u32 RA_5 : 5;
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u32 L_4 : 1;
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u32 dummy3 : 1;
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u32 : 1;
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u32 CRFD_4 : 3;
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u32 OPCD_B : 6;
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};
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struct
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{
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u32 : 16;
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// Segment register
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u32 SR : 4;
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u32 : 1;
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u32 RS_2 : 5;
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@ -131,6 +152,7 @@ union UGeckoInstruction
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{
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u32 Rc_4 : 1;
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u32 SUBOP5 : 5;
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// ?
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u32 RC : 5;
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u32 : 5;
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u32 RA_6 : 5;
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@ -140,7 +162,9 @@ union UGeckoInstruction
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struct
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{ u32 : 10;
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// Overflow enable
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u32 OE : 1;
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// Special-purpose register
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u32 SPR : 10;
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u32 : 11;
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};
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@ -148,7 +172,9 @@ union UGeckoInstruction
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{
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u32 : 10;
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u32 OE_3 : 1;
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// Upper special-purpose register
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u32 SPRU : 5;
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// Lower special-purpose register
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u32 SPRL : 5;
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u32 : 11;
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};
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@ -157,8 +183,11 @@ union UGeckoInstruction
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struct
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{
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u32 Rc_3 : 1;
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// Mask end
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u32 ME : 5;
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// Mask begin
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u32 MB : 5;
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// Shift amount
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u32 SH : 5;
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u32 : 16;
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};
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@ -167,8 +196,11 @@ union UGeckoInstruction
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struct
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{
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u32 : 11;
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// Source bit in the CR
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u32 CRBB : 5;
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// Source bit in the CR
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u32 CRBA : 5;
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// Destination bit in the CR
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u32 CRBD : 5;
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u32 : 6;
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};
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@ -177,6 +209,7 @@ union UGeckoInstruction
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struct
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{
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u32 : 11;
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// Time base register
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u32 TBR : 10;
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u32 : 11;
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};
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@ -184,7 +217,9 @@ union UGeckoInstruction
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struct
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{
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u32 : 11;
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// Upper time base register
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u32 TBRU : 5;
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// Lower time base register
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u32 TBRL : 5;
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u32 : 11;
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};
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@ -192,50 +227,56 @@ union UGeckoInstruction
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struct
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{
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u32 : 18;
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// Source field in the CR or FPSCR
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u32 CRFS : 3;
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u32 : 2;
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u32 CRFD_5 : 3;
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u32 : 6;
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};
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// float
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struct
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{
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u32 : 12;
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// Field mask, identifies the CR fields to be updated by mtcrf
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u32 CRM : 8;
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u32 : 1;
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// Destination FPR
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u32 FD : 5;
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u32 : 6;
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};
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struct
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{
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u32 : 6;
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// Source FPR
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u32 FC : 5;
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// Source FPR
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u32 FB : 5;
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// Source FPR
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u32 FA : 5;
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// Source FPR
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u32 FS : 5;
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u32 : 6;
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};
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struct
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{
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u32 OFS : 16;
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u32 : 16;
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};
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struct
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{
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u32 : 17;
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// Field mask, identifies the FPSCR fields to be updated by mtfsf
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u32 FM : 8;
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u32 : 7;
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};
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// paired
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// paired single quantized load/store
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struct
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{
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u32 : 7;
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// Graphics quantization register to use
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u32 Ix : 3;
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// 0: paired single, 1: scalar
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u32 Wx : 1;
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u32 : 1;
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// Graphics quantization register to use
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u32 I : 3;
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// 0: paired single, 1: scalar
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u32 W : 1;
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u32 : 16;
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};
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@ -248,7 +289,8 @@ union UGeckoInstruction
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struct
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{
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u32 dummyX : 11;
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u32 : 11;
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// Number of bytes to use in lswi/stswi (0 means 32 bytes)
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u32 NB : 5;
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};
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};
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