From e5b5713d7059f52326f45a42fcafbe15c2ae7edc Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@Gmail.com>
Date: Sun, 8 Sep 2013 07:37:03 +0000
Subject: [PATCH] [ARM] Optimize that fastmem load/stores minimally.

---
 .../Src/PowerPC/JitArm32/JitArm_BackPatch.cpp |  5 ++-
 .../Src/PowerPC/JitArm32/JitArm_LoadStore.cpp | 31 ++++++++++---------
 2 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_BackPatch.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_BackPatch.cpp
index a8ea4d929a..d051dae726 100644
--- a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_BackPatch.cpp
+++ b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_BackPatch.cpp
@@ -96,7 +96,7 @@ const u8 *JitArm::BackPatch(u8 *codePtr, u32, void *ctx_void)
 
 	if (Store)
 	{
-		const u32 ARMREGOFFSET = 4 * 7;
+		const u32 ARMREGOFFSET = 4 * 5;
 		ARMXEmitter emitter(codePtr - ARMREGOFFSET);
 		switch (accessSize)
 		{
@@ -117,7 +117,6 @@ const u8 *JitArm::BackPatch(u8 *codePtr, u32, void *ctx_void)
 		emitter.MOV(R1, R10); // Addr- 5 
 		emitter.BL(R14); // 6
 		emitter.POP(4, R0, R1, R2, R3); // 7
-		emitter.NOP(1); // 8
 		u32 newPC = ctx->reg_pc - (ARMREGOFFSET + 4 * 4);
 		ctx->reg_pc = newPC;
 		emitter.FlushIcache();
@@ -125,7 +124,7 @@ const u8 *JitArm::BackPatch(u8 *codePtr, u32, void *ctx_void)
 	}
 	else
 	{
-		const u32 ARMREGOFFSET = 4 * 6;
+		const u32 ARMREGOFFSET = 4 * 4;
 		ARMXEmitter emitter(codePtr - ARMREGOFFSET);
 		switch (accessSize)
 		{
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStore.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStore.cpp
index 391f7b0537..8a12976680 100644
--- a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStore.cpp
+++ b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStore.cpp
@@ -33,16 +33,15 @@
 
 void JitArm::UnsafeStoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 offset)
 {
-
 	// All this gets replaced on backpatch
-	MOVI2R(R14, Memory::MEMVIEW32_MASK, false); // 1-2 
-	AND(dest, dest, R14); // 3
-	MOVI2R(R14, (u32)Memory::base, false); // 4-5
-	ADD(dest, dest, R14); // 6
+	Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
+	BIC(dest, dest, mask); // 1
+	MOVI2R(R14, (u32)Memory::base, false); // 2-3
+	ADD(dest, dest, R14); // 4
 	switch (accessSize)
 	{
 		case 32:
-			REV(value, value); // 7
+			REV(value, value); // 5
 		break;
 		case 16:
 			REV16(value, value);
@@ -54,7 +53,7 @@ void JitArm::UnsafeStoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 o
 	switch (accessSize)
 	{
 		case 32:
-			STR(value, dest); // 8
+			STR(value, dest); // 6
 		break;
 		case 16:
 			STRH(value, dest);
@@ -63,6 +62,7 @@ void JitArm::UnsafeStoreFromReg(ARMReg dest, ARMReg value, int accessSize, s32 o
 			STRB(value, dest);
 		break;
 	}
+	NOP(1); // 7
 }
 
 void JitArm::SafeStoreFromReg(bool fastmem, s32 dest, u32 value, s32 regOffset, int accessSize, s32 offset)
@@ -224,14 +224,14 @@ void JitArm::UnsafeLoadToReg(ARMReg dest, ARMReg addr, int accessSize, s32 offse
 	ADD(addr, addr, rA); // - 1
 
 	// All this gets replaced on backpatch
-	MOVI2R(rA, Memory::MEMVIEW32_MASK, false); // 2 
-	AND(addr, addr, rA); // 3
-	MOVI2R(rA, (u32)Memory::base, false); // 5
-	ADD(addr, addr, rA); // 6
+	Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
+	BIC(addr, addr, mask); // 1
+	MOVI2R(rA, (u32)Memory::base, false); // 2-3
+	ADD(addr, addr, rA); // 4
 	switch (accessSize)
 	{
 		case 32:
-			LDR(dest, addr); // 7
+			LDR(dest, addr); // 5
 		break;
 		case 16:
 			LDRH(dest, addr);
@@ -243,7 +243,7 @@ void JitArm::UnsafeLoadToReg(ARMReg dest, ARMReg addr, int accessSize, s32 offse
 	switch (accessSize)
 	{
 		case 32:
-			REV(dest, dest); // 9
+			REV(dest, dest); // 6
 		break;
 		case 16:
 			REV16(dest, dest);
@@ -253,6 +253,7 @@ void JitArm::UnsafeLoadToReg(ARMReg dest, ARMReg addr, int accessSize, s32 offse
 		break;
 
 	}
+	NOP(2); // 7-8
 	gpr.Unlock(rA);
 }
 
@@ -460,8 +461,8 @@ void JitArm::lmw(UGeckoInstruction inst)
 	MOVI2R(rA, inst.SIMM_16);
 	if (a)
 		ADD(rA, rA, gpr.R(a));
-	MOVI2R(rB, Memory::MEMVIEW32_MASK, false); // 1-2 
-	AND(rA, rA, rB); // 3
+	Operand2 mask(3, 1); // ~(Memory::MEMVIEW32_MASK)
+	BIC(rA, rA, mask); // 3
 	MOVI2R(rB, (u32)Memory::base, false); // 4-5
 	ADD(rA, rA, rB); // 6