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DSPLLE some more exception clean up, still couldn't get zelda to work:(

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git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3623 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
nakeee
2009-06-30 17:33:38 +00:00
parent 22aa9128ee
commit e6d78bcf3c
5 changed files with 28 additions and 17 deletions
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10
Source/Core/DSPCore/Src/DSPAccelerator.cpp
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@ -143,12 +143,12 @@ u16 dsp_read_accelerator()
Address = (gdsp_ifx_regs[DSP_ACSAH] << 16) | gdsp_ifx_regs[DSP_ACSAL];
// Do we really need both?
DSPCore_SetException(3);
DSPCore_SetException(5);
DSPCore_SetException(EXP_4);
DSPCore_SetException(EXP_ACCOV);
// Somehow, YN1 and YN2 must be initialized with their "loop" values, so yeah,
// it seems likely that we should raise an exception to let the DSP program do that,
// at least if DSP_FORMAT == 0x0A.
// Somehow, YN1 and YN2 must be initialized with their "loop" values,
// so yeah, it seems likely that we should raise an exception to let
// the DSP program do that, at least if DSP_FORMAT == 0x0A.
}
gdsp_ifx_regs[DSP_ACCAH] = Address >> 16;

4
Source/Core/DSPCore/Src/DSPCore.cpp
View File

@ -155,10 +155,10 @@ void DSPCore_CheckExternalInterrupt()
// check if there is an external interrupt
if (g_dsp.cr & CR_EXTERNAL_INT)
{
if (dsp_SR_is_flag_set(SR_INT_ENABLE))
if (dsp_SR_is_flag_set(SR_800) && dsp_SR_is_flag_set(SR_INT_ENABLE))
{
// level 7 is the interrupt exception. is it?
DSPCore_SetException(7);
DSPCore_SetException(EXP_INT);
g_dsp.cr &= ~CR_EXTERNAL_INT;
}
}

9
Source/Core/DSPCore/Src/DSPCore.h
View File

@ -161,6 +161,15 @@
// This should be the bits affected by CMP. Does not include logic zero.
#define SR_CMP_MASK 0x3f
// exceptions vector
#define EXP_RESET 0 // 0x0000
#define EXP_STOVF 1 // 0x0002 stack under/over flow
#define EXP_4 2 // 0x0004
#define EXP_6 3 // 0x0006
#define EXP_8 4 // 0x0008
#define EXP_ACCOV 5 // 0x000a accelerator address overflow
#define EXP_c 6 // 0x000c
#define EXP_INT 7 // 0x000e external int? (mail?)
struct SDSP
{

6
Source/Core/DSPCore/Src/DSPHWInterface.cpp
View File

@ -81,7 +81,7 @@ void gdsp_mbox_write_h(u8 mbx, u16 val)
DEBUG_LOG(DSPLLE, " - DSP writes mail to mbx %i: 0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(GDSP_MBOX_DSP), g_dsp.pc);
} else {
// mailbox
DSPCore_SetException(7);
// DSPCore_SetException(EXP_INT);
}
}
@ -101,7 +101,7 @@ void gdsp_mbox_write_l(u8 mbx, u16 val)
DEBUG_LOG(DSPLLE, " - DSP writes mail to mbx %i: 0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(GDSP_MBOX_DSP), g_dsp.pc);
} else {
// mailbox
DSPCore_SetException(7);
DSPCore_SetException(EXP_INT);
}
}
@ -152,7 +152,7 @@ void gdsp_ifx_write(u16 addr, u16 val)
break;
case 0xd3: // ZeldaUnk (accelerator WRITE)
ERROR_LOG(DSPLLE, "Write To ZeldaUnk pc=%04x (%04x)\n", g_dsp.pc, val);
DEBUG_LOG(DSPLLE, "Write To ZeldaUnk pc=%04x (%04x)\n", g_dsp.pc, val);
dsp_write_aram_d3(val);
break;