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JitIL: Fix a bug in floatpoint load/store instructions.
The regBuildMemAddress function already clears the address register. Not only is clearing it again pointless, regBuildMemAddress uses the bits in IInfo slightly diffrently and the second clear can clear the wrong registers causing bugs if something else actually needs to use those registers.
This commit is contained in:
@ -1563,7 +1563,6 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress)
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RI.Jit->SafeLoadToReg(RSCRATCH2, info.first, 32, info.second, regsInUse(RI), false);
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RI.Jit->SafeLoadToReg(RSCRATCH2, info.first, 32, info.second, regsInUse(RI), false);
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Jit->MOVD_xmm(reg, R(RSCRATCH2));
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Jit->MOVD_xmm(reg, R(RSCRATCH2));
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RI.fregs[reg] = I;
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RI.fregs[reg] = I;
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regNormalRegClear(RI, I);
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break;
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break;
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}
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}
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case LoadDouble:
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case LoadDouble:
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@ -1577,7 +1576,6 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress)
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RI.Jit->SafeLoadToReg(RSCRATCH2, info.first, 64, info.second, regsInUse(RI), false);
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RI.Jit->SafeLoadToReg(RSCRATCH2, info.first, 64, info.second, regsInUse(RI), false);
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Jit->MOVQ_xmm(reg, R(RSCRATCH2));
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Jit->MOVQ_xmm(reg, R(RSCRATCH2));
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RI.fregs[reg] = I;
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RI.fregs[reg] = I;
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regNormalRegClear(RI, I);
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break;
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break;
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}
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}
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case LoadPaired:
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case LoadPaired:
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@ -1624,8 +1622,6 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress)
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if (RI.IInfo[I - RI.FirstI] & 4)
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if (RI.IInfo[I - RI.FirstI] & 4)
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fregClearInst(RI, getOp1(I));
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fregClearInst(RI, getOp1(I));
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if (RI.IInfo[I - RI.FirstI] & 8)
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regClearInst(RI, getOp2(I));
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break;
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break;
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}
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}
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case StoreDouble:
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case StoreDouble:
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@ -1646,8 +1642,6 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress)
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if (RI.IInfo[I - RI.FirstI] & 4)
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if (RI.IInfo[I - RI.FirstI] & 4)
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fregClearInst(RI, getOp1(I));
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fregClearInst(RI, getOp1(I));
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if (RI.IInfo[I - RI.FirstI] & 8)
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regClearInst(RI, getOp2(I));
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break;
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break;
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}
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}
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case StorePaired:
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case StorePaired:
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