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JIT: Get rid of SHLs with shifts of 1, 2, 3

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Also contains a few other minor jit code optimizations.

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@7657 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
pierre 2011-06-30 20:25:37 +00:00
parent 383d12185f
commit ea95e603b2
2 changed files with 14 additions and 20 deletions
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20
Source/Core/Core/Src/DSP/Jit/DSPJitBranch.cpp
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@ -40,19 +40,17 @@ static void ReJitConditional(const UDSPInstruction opc, DSPEmitter& emitter)
{ {
case 0x0: // GE - Greater Equal case 0x0: // GE - Greater Equal
case 0x1: // L - Less case 0x1: // L - Less
emitter.MOV(16, R(EDX), R(EAX)); emitter.LEA(16, EDX, MScaled(EAX, SCALE_4, 0));
emitter.SHL(16, R(EDX), Imm8(2));
emitter.XOR(16, R(EAX), R(EDX)); emitter.XOR(16, R(EAX), R(EDX));
emitter.TEST(16, R(EAX), Imm16(8)); emitter.TEST(16, R(EAX), Imm16(8));
break; break;
case 0x2: // G - Greater case 0x2: // G - Greater
case 0x3: // LE - Less Equal case 0x3: // LE - Less Equal
emitter.MOV(16, R(EDX), R(EAX)); emitter.LEA(16, EDX, MScaled(EAX, SCALE_4, 0));
emitter.SHL(16, R(EDX), Imm8(2));
emitter.XOR(16, R(EAX), R(EDX)); emitter.XOR(16, R(EAX), R(EDX));
emitter.SHR(16, R(EDX), Imm8(1)); emitter.LEA(16, EAX, MScaled(EAX, SCALE_2, 0));
emitter.OR(16, R(EAX), R(EDX)); emitter.OR(16, R(EAX), R(EDX));
emitter.TEST(16, R(EAX), Imm16(8)); emitter.TEST(16, R(EAX), Imm16(0x10));
break; break;
case 0x4: // NZ - Not Zero case 0x4: // NZ - Not Zero
case 0x5: // Z - Zero case 0x5: // Z - Zero
@ -68,14 +66,12 @@ static void ReJitConditional(const UDSPInstruction opc, DSPEmitter& emitter)
break; break;
case 0xa: // ? case 0xa: // ?
case 0xb: // ? case 0xb: // ?
emitter.MOV(16, R(EDX), R(EAX)); emitter.LEA(16, EDX, MScaled(EAX, SCALE_2, 0));
emitter.SHR(16, R(EDX), Imm8(1));
emitter.OR(16, R(EAX), R(EDX)); emitter.OR(16, R(EAX), R(EDX));
emitter.SHL(16, R(EDX), Imm8(3)); emitter.LEA(16, EDX, MScaled(EDX, SCALE_8, 0));
emitter.NOT(16, R(EDX));
emitter.AND(16, R(EAX), R(EDX));
emitter.NOT(16, R(EAX)); emitter.NOT(16, R(EAX));
emitter.TEST(16, R(EAX), Imm16(0x10)); emitter.OR(16, R(EAX), R(EDX));
emitter.TEST(16, R(EAX), Imm16(0x20));
break; break;
case 0xc: // LNZ - Logic Not Zero case 0xc: // LNZ - Logic Not Zero
case 0xd: // LZ - Logic Zero case 0xd: // LZ - Logic Zero

14
Source/Core/Core/Src/PowerPC/Jit64IL/IR_X86.cpp
View File

@ -1308,15 +1308,14 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, bool UseProfile, bool Mak
Jit->MOVZX(32, 16, EAX, M(((char *)&GQR(quantreg)) + 2)); Jit->MOVZX(32, 16, EAX, M(((char *)&GQR(quantreg)) + 2));
Jit->MOVZX(32, 8, EDX, R(AL)); Jit->MOVZX(32, 8, EDX, R(AL));
Jit->OR(32, R(EDX), Imm8(w << 3)); Jit->OR(32, R(EDX), Imm8(w << 3));
// FIXME: Fix ModR/M encoding to allow [EDX*4+disp32]! (MComplex can do this, no?)
#ifdef _M_IX86 #ifdef _M_IX86
Jit->SHL(32, R(EDX), Imm8(2)); int addr_scale = SCALE_4;
#else #else
Jit->SHL(32, R(EDX), Imm8(3)); int addr_scale = SCALE_8;
#endif #endif
Jit->MOV(32, R(ECX), regLocForInst(RI, getOp1(I))); Jit->MOV(32, R(ECX), regLocForInst(RI, getOp1(I)));
Jit->ABI_AlignStack(0); Jit->ABI_AlignStack(0);
Jit->CALLptr(MDisp(EDX, (u32)(u64)(((JitIL *)jit)->asm_routines.pairedLoadQuantized))); Jit->CALLptr(MScaled(EDX, addr_scale, (u32)(u64)(((JitIL *)jit)->asm_routines.pairedLoadQuantized)));
Jit->ABI_RestoreStack(0); Jit->ABI_RestoreStack(0);
Jit->MOVAPD(reg, R(XMM0)); Jit->MOVAPD(reg, R(XMM0));
RI.fregs[reg] = I; RI.fregs[reg] = I;
@ -1409,16 +1408,15 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, bool UseProfile, bool Mak
u32 quantreg = *I >> 24; u32 quantreg = *I >> 24;
Jit->MOVZX(32, 16, EAX, M(&PowerPC::ppcState.spr[SPR_GQR0 + quantreg])); Jit->MOVZX(32, 16, EAX, M(&PowerPC::ppcState.spr[SPR_GQR0 + quantreg]));
Jit->MOVZX(32, 8, EDX, R(AL)); Jit->MOVZX(32, 8, EDX, R(AL));
// FIXME: Fix ModR/M encoding to allow [EDX*4+disp32]!
#ifdef _M_IX86 #ifdef _M_IX86
Jit->SHL(32, R(EDX), Imm8(2)); int addr_scale = SCALE_4;
#else #else
Jit->SHL(32, R(EDX), Imm8(3)); int addr_scale = SCALE_8;
#endif #endif
Jit->MOV(32, R(ECX), regLocForInst(RI, getOp2(I))); Jit->MOV(32, R(ECX), regLocForInst(RI, getOp2(I)));
Jit->MOVAPD(XMM0, fregLocForInst(RI, getOp1(I))); Jit->MOVAPD(XMM0, fregLocForInst(RI, getOp1(I)));
Jit->ABI_AlignStack(0); Jit->ABI_AlignStack(0);
Jit->CALLptr(MDisp(EDX, (u32)(u64)(((JitIL *)jit)->asm_routines.pairedStoreQuantized))); Jit->CALLptr(MScaled(EDX, addr_scale, (u32)(u64)(((JitIL *)jit)->asm_routines.pairedStoreQuantized)));
Jit->ABI_RestoreStack(0); Jit->ABI_RestoreStack(0);
if (RI.IInfo[I - RI.FirstI] & 4) if (RI.IInfo[I - RI.FirstI] & 4)
fregClearInst(RI, getOp1(I)); fregClearInst(RI, getOp1(I));