piwalker/dolphin
1
0
Fork 0
mirror of https://github.com/dolphin-emu/dolphin.git synced 2025-07-23 06:09:50 -06:00
Code Issues Packages Projects Releases Wiki Activity

Core: Clean up brace placements

Browse Source
This commit is contained in:
Lioncash
2014-08-30 17:23:13 -04:00
parent 8553b0f27b
commit eb535be874
46 changed files with 262 additions and 206 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
Source/Core/Core/DSP/DSPAssembler.cpp
View File

@ -539,7 +539,9 @@ bool DSPAssembler::VerifyParams(const opc_t *opc, param_t *par, int count, bool
if ((int)par[i].val < value ||
(int)par[i].val > value + get_mask_shifted_down(opc->params[i].mask))
{
if (ext) fprintf(stderr, "(ext) ");
if (ext)
fprintf(stderr, "(ext) ");
fprintf(stderr, "%s (param %i)", cur_line.c_str(), current_param);
ShowError(ERR_INVALID_REGISTER);
}
@ -547,7 +549,9 @@ bool DSPAssembler::VerifyParams(const opc_t *opc, param_t *par, int count, bool
case P_PRG:
if ((int)par[i].val < 0 || (int)par[i].val > 0x3)
{
if (ext) fprintf(stderr, "(ext) ");
if (ext)
fprintf(stderr, "(ext) ");
fprintf(stderr, "%s (param %i)", cur_line.c_str(), current_param);
ShowError(ERR_INVALID_REGISTER);
}
@ -555,52 +559,71 @@ bool DSPAssembler::VerifyParams(const opc_t *opc, param_t *par, int count, bool
case P_ACC:
if ((int)par[i].val < 0x20 || (int)par[i].val > 0x21)
{
if (ext) fprintf(stderr, "(ext) ");
if (par[i].val >= 0x1e && par[i].val <= 0x1f) {
if (ext)
fprintf(stderr, "(ext) ");
if (par[i].val >= 0x1e && par[i].val <= 0x1f)
{
fprintf(stderr, "%i : %s ", code_line, cur_line.c_str());
fprintf(stderr, "WARNING: $ACM%d register used instead of $ACC%d register Line: %d Param: %d Ext: %d\n",
(par[i].val & 1), (par[i].val & 1), code_line, current_param, ext);
}
else if (par[i].val >= 0x1c && par[i].val <= 0x1d) {
else if (par[i].val >= 0x1c && par[i].val <= 0x1d)
{
fprintf(stderr, "WARNING: $ACL%d register used instead of $ACC%d register Line: %d Param: %d\n",
(par[i].val & 1), (par[i].val & 1), code_line, current_param);
}
else
{
ShowError(ERR_WRONG_PARAMETER_ACC);
}
}
break;
case P_ACCM:
if ((int)par[i].val < 0x1e || (int)par[i].val > 0x1f)
{
if (ext) fprintf(stderr, "(ext) ");
if (ext)
fprintf(stderr, "(ext) ");
if (par[i].val >= 0x1c && par[i].val <= 0x1d)
{
fprintf(stderr, "WARNING: $ACL%d register used instead of $ACM%d register Line: %d Param: %d\n",
(par[i].val & 1), (par[i].val & 1), code_line, current_param);
}
else if (par[i].val >= 0x20 && par[i].val <= 0x21)
{
fprintf(stderr, "WARNING: $ACC%d register used instead of $ACM%d register Line: %d Param: %d\n",
(par[i].val & 1), (par[i].val & 1), code_line, current_param);
}
else
{
ShowError(ERR_WRONG_PARAMETER_ACC);
}
}
break;
case P_ACCL:
if ((int)par[i].val < 0x1c || (int)par[i].val > 0x1d)
{
if (ext) fprintf(stderr, "(ext) ");
if (ext)
fprintf(stderr, "(ext) ");
if (par[i].val >= 0x1e && par[i].val <= 0x1f)
{
fprintf(stderr, "%s ", cur_line.c_str());
fprintf(stderr, "WARNING: $ACM%d register used instead of $ACL%d register Line: %d Param: %d\n",
(par[i].val & 1), (par[i].val & 1), code_line, current_param);
}
else if (par[i].val >= 0x20 && par[i].val <= 0x21) {
else if (par[i].val >= 0x20 && par[i].val <= 0x21)
{
fprintf(stderr, "%s ", cur_line.c_str());
fprintf(stderr, "WARNING: $ACC%d register used instead of $ACL%d register Line: %d Param: %d\n",
(par[i].val & 1), (par[i].val & 1), code_line, current_param);
}
else
{
ShowError(ERR_WRONG_PARAMETER_ACC);
}
}
break;
/* case P_ACCM_D: //P_ACC_MID:

4
Source/Core/Core/DSP/DSPCore.cpp
View File

@ -185,10 +185,12 @@ void DSPCore_Shutdown()
core_state = DSPCORE_STOP;
if (dspjit) {
if (dspjit)
{
delete dspjit;
dspjit = nullptr;
}
DSPCore_FreeMemoryPages();
g_dsp_cap.reset();

18
Source/Core/Core/DSP/DSPCore.h
View File

@ -192,25 +192,33 @@ struct DSP_Regs
u16 st[4];
u16 cr;
u16 sr;
union {
union
{
u64 val;
struct {
struct
{
u16 l;
u16 m;
u16 h;
u16 m2;//if this gets in the way, drop it.
};
} prod;
union {
union
{
u32 val;
struct {
u16 l;
u16 h;
};
} ax[2];
union {
union
{
u64 val;
struct {
struct
{
u16 l;
u16 m;
u16 h;

10
Source/Core/Core/DSP/DSPIntArithmetic.cpp
View File

@ -370,7 +370,9 @@ void addr(const UDSPInstruction opc)
s64 acc = dsp_get_long_acc(dreg);
s64 ax = 0;
switch (sreg) {
switch (sreg)
{
case DSP_REG_AXL0:
case DSP_REG_AXL1:
ax = (s16)g_dsp.r.ax[sreg-DSP_REG_AXL0].l;
@ -383,6 +385,7 @@ void addr(const UDSPInstruction opc)
ax = 0;
break;
}
ax <<= 16;
s64 res = acc + ax;
@ -569,7 +572,9 @@ void subr(const UDSPInstruction opc)
s64 acc = dsp_get_long_acc(dreg);
s64 ax = 0;
switch (sreg) {
switch (sreg)
{
case DSP_REG_AXL0:
case DSP_REG_AXL1:
ax = (s16)g_dsp.r.ax[sreg-DSP_REG_AXL0].l;
@ -582,6 +587,7 @@ void subr(const UDSPInstruction opc)
ax = 0;
break;
}
ax <<= 16;
s64 res = acc - ax;

21
Source/Core/Core/DSP/DSPIntCCUtil.cpp
View File

@ -111,31 +111,38 @@ inline int GetMultiplyModifier()
return (g_dsp.r.sr & SR_MUL_MODIFY)?1:2;
}
inline bool isCarry() {
inline bool isCarry()
{
return (g_dsp.r.sr & SR_CARRY) ? true : false;
}
inline bool isOverflow() {
inline bool isOverflow()
{
return (g_dsp.r.sr & SR_OVERFLOW) ? true : false;
}
inline bool isOverS32() {
inline bool isOverS32()
{
return (g_dsp.r.sr & SR_OVER_S32) ? true : false;
}
inline bool isLess() {
inline bool isLess()
{
return (!(g_dsp.r.sr & SR_OVERFLOW) != !(g_dsp.r.sr & SR_SIGN));
}
inline bool isZero() {
inline bool isZero()
{
return (g_dsp.r.sr & SR_ARITH_ZERO) ? true : false;
}
inline bool isLogicZero() {
inline bool isLogicZero()
{
return (g_dsp.r.sr & SR_LOGIC_ZERO) ? true : false;
}
inline bool isConditionA() {
inline bool isConditionA()
{
return (((g_dsp.r.sr & SR_OVER_S32) || (g_dsp.r.sr & SR_TOP2BITS)) && !(g_dsp.r.sr & SR_ARITH_ZERO)) ? true : false;
}

19
Source/Core/Core/DSP/DSPIntCCUtil.h
View File

@ -10,7 +10,8 @@
#include "Common/Common.h"
namespace DSPInterpreter {
namespace DSPInterpreter
{
bool CheckCondition(u8 _Condition);
@ -20,19 +21,23 @@ void Update_SR_Register16(s16 _Value, bool carry = false, bool overflow = false,
void Update_SR_Register64(s64 _Value, bool carry = false, bool overflow = false);
void Update_SR_LZ(bool value);
inline bool isCarry(u64 val, u64 result) {
return (val>result);
inline bool isCarry(u64 val, u64 result)
{
return (val > result);
}
inline bool isCarry2(u64 val, u64 result) {
return (val>=result);
inline bool isCarry2(u64 val, u64 result)
{
return (val >= result);
}
inline bool isOverflow(s64 val1, s64 val2, s64 res) {
inline bool isOverflow(s64 val1, s64 val2, s64 res)
{
return ((val1 ^ res) & (val2 ^ res)) < 0;
}
inline bool isOverS32(s64 acc) {
inline bool isOverS32(s64 acc)
{
return (acc != (s32)acc) ? true : false;
}

21
Source/Core/Core/DSP/Jit/DSPJitArithmetic.cpp
View File

@ -1358,9 +1358,12 @@ void DSPEmitter::lsrn(const UDSPInstruction opc)
// else
// shift = accm & 0x3f;
// if (shift > 0) {
// if (shift > 0)
// {
// acc >>= shift;
// } else if (shift < 0) {
// }
// else if (shift < 0)
// {
// acc <<= -shift;
// }
@ -1414,9 +1417,12 @@ void DSPEmitter::asrn(const UDSPInstruction opc)
// else
// shift = accm & 0x3f;
// if (shift > 0) {
// if (shift > 0)
// {
// acc >>= shift;
// } else if (shift < 0) {
// }
// else if (shift < 0)
// {
// acc <<= -shift;
// }
@ -1474,9 +1480,12 @@ void DSPEmitter::lsrnrx(const UDSPInstruction opc)
// else
// shift = axh & 0x3f;
// if (shift > 0) {
// if (shift > 0)
// {
// acc <<= shift;
// } else if (shift < 0) {
// }
// else if (shift < 0)
// {
// acc >>= -shift;
// }

93
Source/Core/Core/DSP/Jit/DSPJitCCUtil.cpp
View File

@ -133,16 +133,6 @@ void DSPEmitter::Update_SR_Register64_Carry2(X64Reg val, X64Reg carry_ovfl)
Update_SR_Register();
}
//void DSPEmitter::Update_SR_Register16(s16 _Value, bool carry, bool overflow, bool overS32)
//{
// // 0x20 - Checks if top bits of m are equal
// if ((((u16)_Value >> 14) == 0) || (((u16)_Value >> 14) == 3))
// {
// g_dsp.r[DSP_REG_SR] |= SR_TOP2BITS;
// }
//}
// In: RAX: s64 _Value
// Clobbers RDX
void DSPEmitter::Update_SR_Register16(X64Reg val)
@ -205,86 +195,3 @@ void DSPEmitter::Update_SR_Register16_OverS32(Gen::X64Reg val)
//AND(32, R(val), Imm32(0xc0000000));
Update_SR_Register16(val);
}
//void DSPEmitter::Update_SR_LZ(bool value) {
// if (value == true)
// g_dsp.r[DSP_REG_SR] |= SR_LOGIC_ZERO;
// else
// g_dsp.r[DSP_REG_SR] &= ~SR_LOGIC_ZERO;
//}
//inline int GetMultiplyModifier()
//{
// return (g_dsp.r[DSP_REG_SR] & SR_MUL_MODIFY)?1:2;
//}
//inline bool isCarry() {
// return (g_dsp.r[DSP_REG_SR] & SR_CARRY) ? true : false;
//}
//inline bool isOverflow() {
// return (g_dsp.r[DSP_REG_SR] & SR_OVERFLOW) ? true : false;
//}
//inline bool isOverS32() {
// return (g_dsp.r[DSP_REG_SR] & SR_OVER_S32) ? true : false;
//}
//inline bool isLess() {
// return (!(g_dsp.r[DSP_REG_SR] & SR_OVERFLOW) != !(g_dsp.r[DSP_REG_SR] & SR_SIGN));
//}
//inline bool isZero() {
// return (g_dsp.r[DSP_REG_SR] & SR_ARITH_ZERO) ? true : false;
//}
//inline bool isLogicZero() {
// return (g_dsp.r[DSP_REG_SR] & SR_LOGIC_ZERO) ? true : false;
//}
//inline bool isConditionA() {
// return (((g_dsp.r[DSP_REG_SR] & SR_OVER_S32) || (g_dsp.r[DSP_REG_SR] & SR_TOP2BITS)) && !(g_dsp.r[DSP_REG_SR] & SR_ARITH_ZERO)) ? true : false;
//}
//see DSPCore.h for flags
//bool CheckCondition(u8 _Condition)
//{
// switch (_Condition & 0xf)
// {
// case 0xf: // Always true.
// return true;
// case 0x0: // GE - Greater Equal
// return !isLess();
// case 0x1: // L - Less
// return isLess();
// case 0x2: // G - Greater
// return !isLess() && !isZero();
// case 0x3: // LE - Less Equal
// return isLess() || isZero();
// case 0x4: // NZ - Not Zero
// return !isZero();
// case 0x5: // Z - Zero
// return isZero();
// case 0x6: // NC - Not carry
// return !isCarry();
// case 0x7: // C - Carry
// return isCarry();
// case 0x8: // ? - Not over s32
// return !isOverS32();
// case 0x9: // ? - Over s32
// return isOverS32();
// case 0xa: // ?
// return isConditionA();
// case 0xb: // ?
// return !isConditionA();
// case 0xc: // LNZ - Logic Not Zero
// return !isLogicZero();
// case 0xd: // LZ - Logic Zero
// return isLogicZero();
// case 0xe: // 0 - Overflow
// return isOverflow();
// default:
// return true;
// }
//}

6
Source/Core/Core/DSP/Jit/DSPJitExtOps.cpp
View File

@ -115,7 +115,8 @@ void DSPEmitter::l(const UDSPInstruction opc)
pushExtValueFromMem(dreg, sreg);
if (dreg >= DSP_REG_ACM0) {
if (dreg >= DSP_REG_ACM0)
{
//save SR too, so we can decide later.
//even if only for one bit, can only
//store (up to) two registers in EBX,
@ -139,7 +140,8 @@ void DSPEmitter::ln(const UDSPInstruction opc)
pushExtValueFromMem(dreg, sreg);
if (dreg >= DSP_REG_ACM0) {
if (dreg >= DSP_REG_ACM0)
{
//save SR too, so we can decide later.
//even if only for one bit, can only
//store (up to) two registers in EBX,

6
Source/Core/Core/DSP/Jit/DSPJitRegCache.cpp
View File

@ -263,7 +263,8 @@ void DSPJitRegCache::flushRegs(DSPJitRegCache &cache, bool emit)
}
// sync the freely used xregs
if (!emit) {
if (!emit)
{
for (i = 0; i < NUMXREGS; i++)
{
if (cache.xregs[i].guest_reg == DSP_REG_USED &&
@ -501,7 +502,8 @@ void DSPJitRegCache::pushRegs()
emitter.MOV(64, R(RBP), M(&ebp_store));
}
void DSPJitRegCache::popRegs() {
void DSPJitRegCache::popRegs()
{
emitter.MOV(64, M(&ebp_store), R(RBP));
int push_count = 0;
for (X64CachedReg& xreg : xregs)