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VideoCommon/PixelEngine: Refactor to class, move to Core::System.
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@ -3,10 +3,21 @@
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#pragma once
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#include <mutex>
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#include "Common/BitField.h"
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#include "Common/CommonTypes.h"
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class PointerWrap;
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namespace Core
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{
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class System;
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}
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namespace CoreTiming
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{
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struct EventType;
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}
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namespace MMIO
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{
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class Mapping;
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@ -54,14 +65,157 @@ enum class AlphaReadMode : u16
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ReadNone = 2, // Always read the real alpha value
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};
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void Init();
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void DoState(PointerWrap& p);
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// Note: These enums are (assumed to be) identical to the one in BPMemory, but the base type is set
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// to u16 instead of u32 for BitField
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enum class CompareMode : u16
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{
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Never = 0,
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Less = 1,
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Equal = 2,
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LEqual = 3,
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Greater = 4,
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NEqual = 5,
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GEqual = 6,
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Always = 7
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};
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void RegisterMMIO(MMIO::Mapping* mmio, u32 base);
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union UPEZConfReg
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{
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u16 hex = 0;
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BitField<0, 1, bool, u16> z_comparator_enable;
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BitField<1, 3, CompareMode, u16> function;
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BitField<4, 1, bool, u16> z_update_enable;
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};
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// gfx backend support
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void SetToken(const u16 token, const bool interrupt, int cycle_delay);
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void SetFinish(int cycle_delay);
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AlphaReadMode GetAlphaReadMode();
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enum class SrcBlendFactor : u16
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{
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Zero = 0,
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One = 1,
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DstClr = 2,
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InvDstClr = 3,
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SrcAlpha = 4,
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InvSrcAlpha = 5,
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DstAlpha = 6,
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InvDstAlpha = 7
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};
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enum class DstBlendFactor : u16
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{
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Zero = 0,
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One = 1,
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SrcClr = 2,
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InvSrcClr = 3,
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SrcAlpha = 4,
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InvSrcAlpha = 5,
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DstAlpha = 6,
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InvDstAlpha = 7
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};
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enum class LogicOp : u16
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{
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Clear = 0,
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And = 1,
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AndReverse = 2,
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Copy = 3,
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AndInverted = 4,
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NoOp = 5,
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Xor = 6,
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Or = 7,
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Nor = 8,
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Equiv = 9,
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Invert = 10,
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OrReverse = 11,
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CopyInverted = 12,
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OrInverted = 13,
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Nand = 14,
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Set = 15
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};
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union UPEAlphaConfReg
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{
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u16 hex = 0;
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BitField<0, 1, bool, u16> blend; // Set for GX_BM_BLEND or GX_BM_SUBTRACT
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BitField<1, 1, bool, u16> logic; // Set for GX_BM_LOGIC
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BitField<2, 1, bool, u16> dither;
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BitField<3, 1, bool, u16> color_update_enable;
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BitField<4, 1, bool, u16> alpha_update_enable;
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BitField<5, 3, DstBlendFactor, u16> dst_factor;
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BitField<8, 3, SrcBlendFactor, u16> src_factor;
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BitField<11, 1, bool, u16> subtract; // Set for GX_BM_SUBTRACT
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BitField<12, 4, LogicOp, u16> logic_op;
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};
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union UPEDstAlphaConfReg
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{
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u16 hex = 0;
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BitField<0, 8, u8, u16> alpha;
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BitField<8, 1, bool, u16> enable;
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};
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union UPEAlphaModeConfReg
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{
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u16 hex = 0;
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BitField<0, 8, u8, u16> threshold;
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// Yagcd and libogc use 8 bits for this, but the enum only needs 3
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BitField<8, 3, CompareMode, u16> compare_mode;
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};
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union UPEAlphaReadReg
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{
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u16 hex = 0;
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BitField<0, 2, AlphaReadMode, u16> read_mode;
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};
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// fifo Control Register
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union UPECtrlReg
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{
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u16 hex = 0;
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BitField<0, 1, bool, u16> pe_token_enable;
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BitField<1, 1, bool, u16> pe_finish_enable;
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BitField<2, 1, bool, u16> pe_token; // Write only
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BitField<3, 1, bool, u16> pe_finish; // Write only
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};
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class PixelEngineManager
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{
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public:
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void Init();
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void DoState(PointerWrap& p);
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void RegisterMMIO(MMIO::Mapping* mmio, u32 base);
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// gfx backend support
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void SetToken(const u16 token, const bool interrupt, int cycle_delay);
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void SetFinish(int cycle_delay);
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AlphaReadMode GetAlphaReadMode() const { return m_alpha_read.read_mode; }
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private:
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void RaiseEvent(int cycles_into_future);
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void UpdateInterrupts();
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void SetTokenFinish_OnMainThread(Core::System& system, u64 userdata, s64 cycles_late);
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static void SetTokenFinish_OnMainThread_Static(Core::System& system, u64 userdata,
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s64 cycles_late);
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// STATE_TO_SAVE
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UPEZConfReg m_z_conf;
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UPEAlphaConfReg m_alpha_conf;
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UPEDstAlphaConfReg m_dst_alpha_conf;
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UPEAlphaModeConfReg m_alpha_mode_conf;
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UPEAlphaReadReg m_alpha_read;
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UPECtrlReg m_control;
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std::mutex m_token_finish_mutex;
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u16 m_token = 0;
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u16 m_token_pending = 0;
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bool m_token_interrupt_pending = false;
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bool m_finish_interrupt_pending = false;
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bool m_event_raised = false;
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bool m_signal_token_interrupt = false;
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bool m_signal_finish_interrupt = false;
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CoreTiming::EventType* m_event_type_set_token_finish = nullptr;
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};
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} // namespace PixelEngine
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