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Fix the addresses of MMIO registers.

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MMIO registers are located at 0x0C000000 and 0x0D000000, not 0xCC000000.
The 0xCC000000 addresses are just an artifact of address translation.
This commit is contained in:
magumagu
2015-02-11 18:01:47 -08:00
parent 5b6a947e8f
commit f316265973
8 changed files with 202 additions and 163 deletions
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58
Source/UnitTests/Core/MMIOTest.cpp
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@ -9,13 +9,13 @@
TEST(UniqueID, UniqueEnough)
{
std::unordered_set<u32> ids;
for (u32 i = 0xCC000000; i < 0xCC010000; ++i)
for (u32 i = 0x0C000000; i < 0x0C010000; ++i)
{
u32 unique_id = MMIO::UniqueID(i);
EXPECT_EQ(ids.end(), ids.find(unique_id));
ids.insert(unique_id);
}
for (u32 i = 0xCD000000; i < 0xCD010000; ++i)
for (u32 i = 0x0D000000; i < 0x0D010000; ++i)
{
u32 unique_id = MMIO::UniqueID(i);
EXPECT_EQ(ids.end(), ids.find(unique_id));
@ -29,18 +29,22 @@ TEST(IsMMIOAddress, SpecialAddresses)
SConfig::GetInstance().m_LocalCoreStartupParameter.bWii = true;
// WG Pipe address, should not be handled by MMIO.
EXPECT_FALSE(MMIO::IsMMIOAddress(0xCC008000));
EXPECT_FALSE(MMIO::IsMMIOAddress(0x0C008000));
// Memory zone used by games using the "MMU Speedhack".
// Locked L1 cache allocation.
EXPECT_FALSE(MMIO::IsMMIOAddress(0xE0000000));
// Uncached mirror of MEM1, shouldn't be handled by MMIO
EXPECT_FALSE(MMIO::IsMMIOAddress(0xC0000000));
// Effective address of an MMIO register; MMIO only deals with physical
// addresses.
EXPECT_FALSE(MMIO::IsMMIOAddress(0xCC0000E0));
// And lets check some valid addresses too
EXPECT_TRUE(MMIO::IsMMIOAddress(0xCC0000E0)); // Gamecube MMIOs
EXPECT_TRUE(MMIO::IsMMIOAddress(0xCD00008C)); // Wii MMIOs
EXPECT_TRUE(MMIO::IsMMIOAddress(0xCD800F10)); // Mirror of Wii MMIOs
EXPECT_TRUE(MMIO::IsMMIOAddress(0x0C0000E0)); // Gamecube MMIOs
EXPECT_TRUE(MMIO::IsMMIOAddress(0x0D00008C)); // Wii MMIOs
EXPECT_TRUE(MMIO::IsMMIOAddress(0x0D800F10)); // Mirror of Wii MMIOs
SConfig::Shutdown();
}
@ -63,13 +67,13 @@ protected:
TEST_F(MappingTest, ReadConstant)
{
m_mapping->Register(0xCC001234, MMIO::Constant<u8>(0x42), MMIO::Nop<u8>());
m_mapping->Register(0xCC001234, MMIO::Constant<u16>(0x1234), MMIO::Nop<u16>());
m_mapping->Register(0xCC001234, MMIO::Constant<u32>(0xdeadbeef), MMIO::Nop<u32>());
m_mapping->Register(0x0C001234, MMIO::Constant<u8>(0x42), MMIO::Nop<u8>());
m_mapping->Register(0x0C001234, MMIO::Constant<u16>(0x1234), MMIO::Nop<u16>());
m_mapping->Register(0x0C001234, MMIO::Constant<u32>(0xdeadbeef), MMIO::Nop<u32>());
u8 val8 = m_mapping->Read<u8>(0xCC001234);
u16 val16 = m_mapping->Read<u16>(0xCC001234);
u32 val32 = m_mapping->Read<u32>(0xCC001234);
u8 val8 = m_mapping->Read<u8>(0x0C001234);
u16 val16 = m_mapping->Read<u16>(0x0C001234);
u32 val32 = m_mapping->Read<u32>(0x0C001234);
EXPECT_EQ(0x42, val8);
EXPECT_EQ(0x1234, val16);
@ -82,19 +86,19 @@ TEST_F(MappingTest, ReadWriteDirect)
u16 target_16 = 0;
u32 target_32 = 0;
m_mapping->Register(0xCC001234, MMIO::DirectRead<u8>(&target_8), MMIO::DirectWrite<u8>(&target_8));
m_mapping->Register(0xCC001234, MMIO::DirectRead<u16>(&target_16), MMIO::DirectWrite<u16>(&target_16));
m_mapping->Register(0xCC001234, MMIO::DirectRead<u32>(&target_32), MMIO::DirectWrite<u32>(&target_32));
m_mapping->Register(0x0C001234, MMIO::DirectRead<u8>(&target_8), MMIO::DirectWrite<u8>(&target_8));
m_mapping->Register(0x0C001234, MMIO::DirectRead<u16>(&target_16), MMIO::DirectWrite<u16>(&target_16));
m_mapping->Register(0x0C001234, MMIO::DirectRead<u32>(&target_32), MMIO::DirectWrite<u32>(&target_32));
for (u32 i = 0; i < 100; ++i)
{
u8 val8 = m_mapping->Read<u8>(0xCC001234); EXPECT_EQ(i, val8);
u16 val16 = m_mapping->Read<u16>(0xCC001234); EXPECT_EQ(i, val16);
u32 val32 = m_mapping->Read<u32>(0xCC001234); EXPECT_EQ(i, val32);
u8 val8 = m_mapping->Read<u8>(0x0C001234); EXPECT_EQ(i, val8);
u16 val16 = m_mapping->Read<u16>(0x0C001234); EXPECT_EQ(i, val16);
u32 val32 = m_mapping->Read<u32>(0x0C001234); EXPECT_EQ(i, val32);
val8 += 1; m_mapping->Write(0xCC001234, val8);
val16 += 1; m_mapping->Write(0xCC001234, val16);
val32 += 1; m_mapping->Write(0xCC001234, val32);
val8 += 1; m_mapping->Write(0x0C001234, val8);
val16 += 1; m_mapping->Write(0x0C001234, val16);
val32 += 1; m_mapping->Write(0x0C001234, val32);
}
}
@ -102,21 +106,21 @@ TEST_F(MappingTest, ReadWriteComplex)
{
bool read_called = false, write_called = false;
m_mapping->Register(0xCC001234,
m_mapping->Register(0x0C001234,
MMIO::ComplexRead<u8>([&read_called](u32 addr) {
EXPECT_EQ(0xCC001234, addr);
EXPECT_EQ(0x0C001234, addr);
read_called = true;
return 0x12;
}),
MMIO::ComplexWrite<u8>([&write_called](u32 addr, u8 val) {
EXPECT_EQ(0xCC001234, addr);
EXPECT_EQ(0x0C001234, addr);
EXPECT_EQ(0x34, val);
write_called = true;
})
);
u8 val = m_mapping->Read<u8>(0xCC001234); EXPECT_EQ(0x12, val);
m_mapping->Write(0xCC001234, (u8)0x34);
u8 val = m_mapping->Read<u8>(0x0C001234); EXPECT_EQ(0x12, val);
m_mapping->Write(0x0C001234, (u8)0x34);
EXPECT_TRUE(read_called);
EXPECT_TRUE(write_called);