mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-07-23 14:19:46 -06:00
filled up opcode table as much as I could, commented about opcodes we need to add to the table.
We are still missing tons of opcodes which I'm not sure where to put... git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2825 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
@ -82,6 +82,7 @@ s8 GetMultiplyModifier()
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return(2);
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}
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// TODO add case comments
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bool CheckCondition(u8 _Condition)
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{
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bool taken = false;
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@ -166,7 +167,7 @@ bool CheckCondition(u8 _Condition)
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break;
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default:
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// DEBUG_LOG(DSPHLE, "Unknown condition check: 0x%04x\n", _Condition & 0xf);
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ERROR_LOG(DSPHLE, "Unknown condition check: 0x%04x\n", _Condition & 0xf);
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break;
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}
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@ -178,7 +179,7 @@ bool CheckCondition(u8 _Condition)
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void unknown(const UDSPInstruction& opc)
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{
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//_assert_msg_(MASTER_LOG, !g_dsp.exception_in_progress_hack, "assert while exception");
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ERROR_LOG(DSPHLE, "LLE: Unrecognized opcode %d", opc.hex);
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ERROR_LOG(DSPHLE, "LLE: Unrecognized opcode 0x%04x", opc.hex);
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//g_dsp.pc = g_dsp.err_pc;
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}
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@ -193,6 +194,7 @@ void call(const UDSPInstruction& opc)
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}
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}
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// The code for all ifs?
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void ifcc(const UDSPInstruction& opc)
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{
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if (!CheckCondition(opc.hex & 0xf))
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@ -201,6 +203,7 @@ void ifcc(const UDSPInstruction& opc)
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}
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}
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// The code for all jumps?
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void jcc(const UDSPInstruction& opc)
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{
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u16 dest = dsp_fetch_code();
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@ -212,6 +215,7 @@ void jcc(const UDSPInstruction& opc)
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}
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// FIXME inside
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// FIXME add to opcode table
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void jmpa(const UDSPInstruction& opc)
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{
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u8 reg;
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@ -361,7 +365,7 @@ void lrr(const UDSPInstruction& opc)
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g_dsp.r[sreg]++;
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break;
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case 0x3:
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case 0x3: // LRRN
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g_dsp.r[sreg] += g_dsp.r[sreg + 4];
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break;
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}
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@ -406,20 +410,20 @@ void ilrr(const UDSPInstruction& opc)
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switch ((opc.hex >> 2) & 0x3)
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{
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case 0x0: // no change
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case 0x0: // no change (ILRR)
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break;
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case 0x1: // post decrement
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case 0x1: // post decrement (ILRRD?)
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g_dsp.r[reg]--;
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break;
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case 0x2: // post increment
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case 0x2: // post increment (ILRRI)
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g_dsp.r[reg]++;
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break;
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default:
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// FIXME: Implement
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ERROR_LOG(DSPHLE, "dsp_opc.hex_ilrr");
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ERROR_LOG(DSPHLE, "Unknown ILRR: 0x%04x\n", (opc.hex >> 2) & 0x3);
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}
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}
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@ -510,6 +514,7 @@ void mulcmv(const UDSPInstruction& opc)
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ERROR_LOG(DSPHLE, "dsp_opc.hex_mulcmv ni");
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}
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//TODO: add to opcode table
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void cmpar(const UDSPInstruction& opc)
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{
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u8 rreg = ((opc.hex >> 12) & 0x1) + 0x1a;
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@ -532,6 +537,7 @@ void cmp(const UDSPInstruction& opc)
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Update_SR_Register(acc0 - acc1);
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}
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//TODO: add to opcode table
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void tsta(const UDSPInstruction& opc)
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{
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u8 reg = (opc.hex >> 11) & 0x1;
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@ -555,6 +561,7 @@ void addaxl(const UDSPInstruction& opc)
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Update_SR_Register(acc);
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}
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//TODO: add to opcode table
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void addarn(const UDSPInstruction& opc)
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{
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u8 dreg = opc.hex & 0x3;
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@ -669,6 +676,7 @@ void nx(const UDSPInstruction& opc)
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// FIXME inside
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// TODO: add to opcode table
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void andfc(const UDSPInstruction& opc)
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{
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if (opc.hex & 0xf)
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@ -719,6 +727,7 @@ void andf(const UDSPInstruction& opc)
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}
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// FIXME inside
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// TODO: add to opcode table
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void subf(const UDSPInstruction& opc)
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{
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if (opc.hex & 0xf)
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@ -911,6 +920,7 @@ void neg(const UDSPInstruction& opc)
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}
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// TODO: Implement
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// FIXME: add to opcode table
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void movnp(const UDSPInstruction& opc)
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{
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// UNIMPLEMENTED
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@ -1039,6 +1049,7 @@ void asr16(const UDSPInstruction& opc)
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Update_SR_Register(acc);
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}
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// TODO: add to opcode table
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void shifti(const UDSPInstruction& opc)
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{
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// direction: left
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@ -1131,6 +1142,7 @@ void sbset(const UDSPInstruction& opc)
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// FIXME inside
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// TODO: add to opcode table
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void srbith(const UDSPInstruction& opc)
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{
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switch ((opc.hex >> 8) & 0xf)
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