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BPMemory: Expose more register descriptions for FifoPlayer
This commit is contained in:
NeoBrainX
parent
2cd415dd83
commit
f7b0c8684b
@ -55,6 +55,11 @@ void GetBPRegInfo(const u8* data, char* name, size_t name_size, char* desc, size
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snprintf(name, name_size, #reg); \
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(void)(reg);
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case BPMEM_GENMODE: // 0x00
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SetRegName(BPMEM_GENMODE);
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// TODO: Description
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break;
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case BPMEM_DISPLAYCOPYFILER: // 0x01
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// TODO: This is actually the sample pattern used for copies from an antialiased EFB
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SetRegName(BPMEM_DISPLAYCOPYFILER);
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@ -75,6 +80,28 @@ void GetBPRegInfo(const u8* data, char* name, size_t name_size, char* desc, size
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}
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break;
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case BPMEM_BLENDMODE: // 0x41
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{
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SetRegName(BPMEM_BLENDMODE);
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BlendMode mode; mode.hex = cmddata;
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const char* dstfactors[] = { "0", "1", "src_color", "1-src_color", "src_alpha", "1-src_alpha", "dst_alpha", "1-dst_alpha" };
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const char* srcfactors[] = { "0", "1", "dst_color", "1-dst_color", "src_alpha", "1-src_alpha", "dst_alpha", "1-dst_alpha" };
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const char* logicmodes[] = { "0", "s & d", "s & ~d", "s", "~s & d", "d", "s ^ d", "s | d", "~(s | d)", "~(s ^ d)", "~d", "s | ~d", "~s", "~s | d", "~(s & d)", "1" };
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snprintf(desc, desc_size, "Enable: %s\n"
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"Logic ops: %s\n"
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"Dither: %s\n"
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"Color write: %s\n"
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"Alpha write: %s\n"
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"Dest factor: %s\n"
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"Source factor: %s\n"
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"Subtract: %s\n"
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"Logic mode: %s\n",
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no_yes[mode.blendenable], no_yes[mode.logicopenable], no_yes[mode.dither],
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no_yes[mode.colorupdate], no_yes[mode.alphaupdate], dstfactors[mode.dstfactor],
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srcfactors[mode.srcfactor], no_yes[mode.subtract], logicmodes[mode.logicmode]);
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}
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break;
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case BPMEM_EFB_BR: // 0x4A
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{
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// TODO: Misleading name, should be BPMEM_EFB_WH instead
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@ -148,7 +175,113 @@ void GetBPRegInfo(const u8* data, char* name, size_t name_size, char* desc, size
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// TODO: Description
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break;
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#undef SET_REG_NAME
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case BPMEM_TEV_COLOR_ENV: // 0xC0
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case BPMEM_TEV_COLOR_ENV+2:
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case BPMEM_TEV_COLOR_ENV+4:
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case BPMEM_TEV_COLOR_ENV+8:
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case BPMEM_TEV_COLOR_ENV+10:
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case BPMEM_TEV_COLOR_ENV+12:
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case BPMEM_TEV_COLOR_ENV+14:
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case BPMEM_TEV_COLOR_ENV+16:
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case BPMEM_TEV_COLOR_ENV+18:
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case BPMEM_TEV_COLOR_ENV+20:
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case BPMEM_TEV_COLOR_ENV+22:
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case BPMEM_TEV_COLOR_ENV+24:
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case BPMEM_TEV_COLOR_ENV+26:
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case BPMEM_TEV_COLOR_ENV+28:
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case BPMEM_TEV_COLOR_ENV+30:
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{
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SetRegName(BPMEM_TEV_COLOR_ENV);
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TevStageCombiner::ColorCombiner cc; cc.hex = cmddata;
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const char* tevin[] =
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{
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"prev.rgb", "prev.aaa",
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"c0.rgb", "c0.aaa",
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"c1.rgb", "c1.aaa",
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"c2.rgb", "c2.aaa",
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"tex.rgb", "tex.aaa",
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"ras.rgb", "ras.aaa",
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"ONE", "HALF", "konst.rgb", "ZERO",
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};
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const char* tevbias[] = { "0", "+0.5", "-0.5", "compare" };
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const char* tevop[] = { "add", "sub" };
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const char* tevscale[] = { "1", "2", "4", "0.5" };
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const char* tevout[] = { "prev.rgb", "c0.rgb", "c1.rgb", "c2.rgb" };
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snprintf(desc, desc_size, "tev stage: %d\n"
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"a: %s\n"
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"b: %s\n"
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"c: %s\n"
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"d: %s\n"
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"bias: %s\n"
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"op: %s\n"
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"clamp: %s\n"
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"scale factor: %s\n"
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"dest: %s\n",
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(data[0] - BPMEM_TEV_COLOR_ENV)/2, tevin[cc.a], tevin[cc.b], tevin[cc.c], tevin[cc.d],
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tevbias[cc.bias], tevop[cc.op], no_yes[cc.clamp], tevscale[cc.shift], tevout[cc.dest]);
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break;
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}
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case BPMEM_TEV_ALPHA_ENV: // 0xC1
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case BPMEM_TEV_ALPHA_ENV+2:
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case BPMEM_TEV_ALPHA_ENV+4:
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case BPMEM_TEV_ALPHA_ENV+6:
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case BPMEM_TEV_ALPHA_ENV+8:
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case BPMEM_TEV_ALPHA_ENV+10:
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case BPMEM_TEV_ALPHA_ENV+12:
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case BPMEM_TEV_ALPHA_ENV+14:
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case BPMEM_TEV_ALPHA_ENV+16:
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case BPMEM_TEV_ALPHA_ENV+18:
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case BPMEM_TEV_ALPHA_ENV+20:
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case BPMEM_TEV_ALPHA_ENV+22:
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case BPMEM_TEV_ALPHA_ENV+24:
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case BPMEM_TEV_ALPHA_ENV+26:
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case BPMEM_TEV_ALPHA_ENV+28:
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case BPMEM_TEV_ALPHA_ENV+30:
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{
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SetRegName(BPMEM_TEV_ALPHA_ENV);
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TevStageCombiner::AlphaCombiner ac; ac.hex = cmddata;
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const char* tevin[] =
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{
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"prev", "c0", "c1", "c2",
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"tex", "ras", "konst", "ZERO",
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};
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const char* tevbias[] = { "0", "+0.5", "-0.5", "compare" };
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const char* tevop[] = { "add", "sub" };
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const char* tevscale[] = { "1", "2", "4", "0.5" };
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const char* tevout[] = { "prev", "c0", "c1", "c2" };
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snprintf(desc, desc_size, "tev stage: %d\n"
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"a: %s\n"
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"b: %s\n"
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"c: %s\n"
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"d: %s\n"
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"bias: %s\n"
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"op: %s\n"
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"clamp: %s\n"
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"scale factor: %s\n"
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"dest: %s\n"
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"ras sel: %d\n"
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"tex sel: %d\n",
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(data[0] - BPMEM_TEV_ALPHA_ENV)/2, tevin[ac.a], tevin[ac.b], tevin[ac.c], tevin[ac.d],
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tevbias[ac.bias], tevop[ac.op], no_yes[ac.clamp], tevscale[ac.shift], tevout[ac.dest],
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ac.rswap, ac.tswap);
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break;
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}
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case BPMEM_ALPHACOMPARE: // 0xF3
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{
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SetRegName(BPMEM_ALPHACOMPARE);
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AlphaTest test; test.hex = cmddata;
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const char* functions[] = { "NEVER", "LESS", "EQUAL", "LEQUAL", "GREATER", "NEQUAL", "GEQUAL", "ALWAYS" };
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const char* logic[] = { "AND", "OR", "XOR", "XNOR" };
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snprintf(desc, desc_size, "test 1: %s (ref: %#02x)\n"
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"test 2: %s (ref: %#02x)\n"
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"logic: %s\n",
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functions[test.comp0], test.ref0, functions[test.comp1], test.ref1, logic[test.logic]);
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break;
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}
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#undef SetRegName
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}
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}
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