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Merge pull request #10692 from Pokechu22/dsp-manual-set40-and-write-backlog
docs/DSP: Add sections on 16-bit and 40-bit modes and on main and extended opcode writing to the same register
This commit is contained in:
Mai M
@ -45,7 +45,7 @@ void Interpreter::clrl(const UDSPInstruction opc)
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//----
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// ANDCF $acD.m, #I
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// 0000 001r 1100 0000
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// 0000 001d 1100 0000
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// iiii iiii iiii iiii
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// Set logic zero (LZ) flag in status register $sr if result of logic AND of
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// accumulator mid part $acD.m with immediate value I is equal to I.
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@ -61,7 +61,7 @@ void Interpreter::andcf(const UDSPInstruction opc)
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}
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// ANDF $acD.m, #I
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// 0000 001r 1010 0000
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// 0000 001d 1010 0000
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// iiii iiii iiii iiii
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// Set logic zero (LZ) flag in status register $sr if result of logical AND
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// operation of accumulator mid part $acD.m with immediate value I is equal
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@ -81,7 +81,7 @@ void Interpreter::andf(const UDSPInstruction opc)
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// TST
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// 1011 r001 xxxx xxxx
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// Test accumulator %acR.
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// Test accumulator $acR.
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//
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// flags out: --xx xx00
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void Interpreter::tst(const UDSPInstruction opc)
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@ -143,11 +143,12 @@ void Interpreter::cmpaxh(const UDSPInstruction opc)
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ZeroWriteBackLog();
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}
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// CMPI $amD, #I
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// 0000 001r 1000 0000
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// CMPI $acD, #I
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// 0000 001d 1000 0000
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// iiii iiii iiii iiii
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// Compares mid accumulator $acD.hm ($amD) with sign extended immediate value I.
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// Although flags are being set regarding whole accumulator register.
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// Compares accumulator with immediate. Comparison is executed
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// by subtracting the immediate (16-bit sign extended) from mid accumulator
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// $acD.hm and computing flags based on whole accumulator $acD.
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//
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// flags out: x-xx xxxx
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void Interpreter::cmpi(const UDSPInstruction opc)
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@ -166,8 +167,8 @@ void Interpreter::cmpi(const UDSPInstruction opc)
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// CMPIS $acD, #I
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// 0000 011d iiii iiii
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// Compares accumulator with short immediate. Comaprison is executed
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// by subtracting short immediate (8bit sign extended) from mid accumulator
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// Compares accumulator with short immediate. Comparison is executed
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// by subtracting the short immediate (8-bit sign extended) from mid accumulator
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// $acD.hm and computing flags based on whole accumulator $acD.
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//
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// flags out: x-xx xxxx
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@ -320,7 +321,7 @@ void Interpreter::notc(const UDSPInstruction opc)
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}
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// XORI $acD.m, #I
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// 0000 001r 0010 0000
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// 0000 001d 0010 0000
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// iiii iiii iiii iiii
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// Logic exclusive or (XOR) of accumulator mid part $acD.m with
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// immediate value I.
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@ -337,7 +338,7 @@ void Interpreter::xori(const UDSPInstruction opc)
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}
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// ANDI $acD.m, #I
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// 0000 001r 0100 0000
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// 0000 001d 0100 0000
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// iiii iiii iiii iiii
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// Logic AND of accumulator mid part $acD.m with immediate value I.
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//
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@ -354,7 +355,7 @@ void Interpreter::andi(const UDSPInstruction opc)
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}
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// ORI $acD.m, #I
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// 0000 001r 0110 0000
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// 0000 001d 0110 0000
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// iiii iiii iiii iiii
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// Logic OR of accumulator mid part $acD.m with immediate value I.
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//
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@ -489,8 +490,8 @@ void Interpreter::addaxl(const UDSPInstruction opc)
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UpdateSR64Add(acc, acx, GetLongAcc(dreg));
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}
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// ADDI $amR, #I
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// 0000 001r 0000 0000
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// ADDI $acD, #I
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// 0000 001d 0000 0000
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// iiii iiii iiii iiii
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// Adds immediate (16-bit sign extended) to mid accumulator $acD.hm.
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//
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@ -16,8 +16,23 @@
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namespace DSP::Interpreter
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{
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// Not needed for game ucodes (it slows down interpreter + easier to compare int VS
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// dspjit64 without it)
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// Correctly handle instructions such as `INC'L $ac0 : $ac0.l, @$ar0` (encoded as 0x7660) where both
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// the main opcode and the extension opcode modify the same register. See the "Extended opcodes"
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// section in the manual for more details. No official uCode writes to the same register twice like
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// this, so we don't emulate it by default (and also don't support it in the recompiler).
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//
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// Dolphin only supports this behavior in the interpreter when PRECISE_BACKLOG is defined.
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// In ExecuteInstruction, if an extended opcode is in use, the extended opcode's behavior is
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// executed first, followed by the main opcode's behavior. The extended opcode does not directly
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// write to registers, but instead records the writes into a backlog (WriteToBackLog). The main
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// opcode calls ZeroWriteBackLog after it is done reading the register values; this directly
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// writes zero to all registers that have pending writes in the backlog. The main opcode then is
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// free to write directly to registers it changes. Afterwards, ApplyWriteBackLog bitwise-ors the
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// value of the register and the value in the backlog; if the main opcode didn't write to the
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// register then ZeroWriteBackLog means that the pending value is being or'd with zero, so it's
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// used without changes. When PRECISE_BACKLOG is not defined, ZeroWriteBackLog does nothing and
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// ApplyWriteBackLog overwrites the register value with the value from the backlog (so writes from
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// extended opcodes "win" over the main opcode).
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//#define PRECISE_BACKLOG
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Interpreter::Interpreter(DSPCore& dsp) : m_dsp_core{dsp}
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@ -809,7 +824,7 @@ void Interpreter::ConditionalExtendAccum(int reg)
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void Interpreter::ApplyWriteBackLog()
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{
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// Always make sure to have an extra entry at the end w/ -1 to avoid
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// infinitive loops
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// infinite loops
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for (int i = 0; m_write_back_log_idx[i] != -1; i++)
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{
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u16 value = m_write_back_log[i];
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@ -823,6 +838,11 @@ void Interpreter::ApplyWriteBackLog()
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}
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}
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// The ext ops are calculated in parallel with the actual op. That means that
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// both the main op and the ext op see the same register state as input. The
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// output is simple as long as the main and ext ops don't change the same
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// register. If they do the output is the bitwise OR of the result of both the
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// main and ext ops.
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void Interpreter::WriteToBackLog(int i, int idx, u16 value)
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{
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m_write_back_log[i] = value;
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@ -840,7 +860,7 @@ void Interpreter::ZeroWriteBackLog()
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{
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#ifdef PRECISE_BACKLOG
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// always make sure to have an extra entry at the end w/ -1 to avoid
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// infinitive loops
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// infinite loops
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for (int i = 0; m_write_back_log_idx[i] != -1; i++)
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{
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OpWriteRegister(m_write_back_log_idx[i], 0);
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@ -235,11 +235,6 @@ private:
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void ConditionalExtendAccum(int reg);
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// The ext ops are calculated in parallel with the actual op. That means that
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// both the main op and the ext op see the same register state as input. The
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// output is simple as long as the main and ext ops don't change the same
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// register. If they do the output is the bitwise OR of the result of both the
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// main and ext ops.
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void WriteToBackLog(int i, int idx, u16 value);
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void ZeroWriteBackLog();
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void ZeroWriteBackLogPreserveAcc(u8 acc);
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@ -53,7 +53,7 @@ void DSPEmitter::clrl(const UDSPInstruction opc)
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//----
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// ANDCF $acD.m, #I
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// 0000 001r 1100 0000
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// 0000 001d 1100 0000
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// iiii iiii iiii iiii
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// Set logic zero (LZ) flag in status register $sr if result of logic AND of
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// accumulator mid part $acD.m with immediate value I is equal to I.
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@ -88,7 +88,7 @@ void DSPEmitter::andcf(const UDSPInstruction opc)
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}
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// ANDF $acD.m, #I
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// 0000 001r 1010 0000
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// 0000 001d 1010 0000
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// iiii iiii iiii iiii
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// Set logic zero (LZ) flag in status register $sr if result of logical AND
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// operation of accumulator mid part $acD.m with immediate value I is equal
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@ -126,7 +126,7 @@ void DSPEmitter::andf(const UDSPInstruction opc)
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// TST
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// 1011 r001 xxxx xxxx
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// Test accumulator %acR.
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// Test accumulator $acR.
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//
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// flags out: --xx xx00
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void DSPEmitter::tst(const UDSPInstruction opc)
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@ -220,11 +220,12 @@ void DSPEmitter::cmpaxh(const UDSPInstruction opc)
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}
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}
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// CMPI $amD, #I
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// 0000 001r 1000 0000
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// CMPI $acD, #I
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// 0000 001d 1000 0000
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// iiii iiii iiii iiii
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// Compares mid accumulator $acD.hm ($amD) with sign extended immediate value I.
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// Although flags are being set regarding whole accumulator register.
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// Compares accumulator with immediate. Comparison is executed
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// by subtracting the immediate (16-bit sign extended) from mid accumulator
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// $acD.hm and computing flags based on whole accumulator $acD.
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//
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// flags out: x-xx xxxx
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void DSPEmitter::cmpi(const UDSPInstruction opc)
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@ -257,7 +258,7 @@ void DSPEmitter::cmpi(const UDSPInstruction opc)
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// CMPIS $acD, #I
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// 0000 011d iiii iiii
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// Compares accumulator with short immediate. Comparison is executed
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// by subtracting short immediate (8bit sign extended) from mid accumulator
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// by subtracting the short immediate (8-bit sign extended) from mid accumulator
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// $acD.hm and computing flags based on whole accumulator $acD.
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//
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// flags out: x-xx xxxx
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@ -472,7 +473,7 @@ void DSPEmitter::notc(const UDSPInstruction opc)
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}
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// XORI $acD.m, #I
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// 0000 001r 0010 0000
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// 0000 001d 0010 0000
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// iiii iiii iiii iiii
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// Logic exclusive or (XOR) of accumulator mid part $acD.m with
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// immediate value I.
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@ -498,7 +499,7 @@ void DSPEmitter::xori(const UDSPInstruction opc)
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}
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// ANDI $acD.m, #I
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// 0000 001r 0100 0000
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// 0000 001d 0100 0000
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// iiii iiii iiii iiii
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// Logic AND of accumulator mid part $acD.m with immediate value I.
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//
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@ -523,7 +524,7 @@ void DSPEmitter::andi(const UDSPInstruction opc)
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}
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// ORI $acD.m, #I
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// 0000 001r 0110 0000
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// 0000 001d 0110 0000
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// iiii iiii iiii iiii
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// Logic OR of accumulator mid part $acD.m with immediate value I.
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//
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@ -706,8 +707,8 @@ void DSPEmitter::addaxl(const UDSPInstruction opc)
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}
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}
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// ADDI $amR, #I
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// 0000 001r 0000 0000
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// ADDI $acD, #I
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// 0000 001d 0000 0000
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// iiii iiii iiii iiii
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// Adds immediate (16-bit sign extended) to mid accumulator $acD.hm.
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//
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202
Source/DSPSpy/tests/40bit_ins_test.ds
Normal file
202
Source/DSPSpy/tests/40bit_ins_test.ds
Normal file
@ -0,0 +1,202 @@
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; This test covers the behavior of 40-bit mode with various instructions.
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incdir "tests"
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include "dsp_base.inc"
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positive_value: EQU #0x1234
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negative_value: EQU #0x9876
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negative_imem_value_addr:
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CW negative_value
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; DSPSpy doesn't pre-populating DMEM currently, so instead use these addresses to store values.
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positive_dmem_value_addr: EQU #0x100
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negative_dmem_value_addr: EQU #0x101
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readback_dmem_addr: EQU #0x102
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test_main:
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LRI $ar0, #positive_dmem_value_addr
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LRI $ar1, #negative_dmem_value_addr
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LRI $ar2, #negative_imem_value_addr
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LRI $ar3, #readback_dmem_addr
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LRI $ix0, #0
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LRI $ix1, #0
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LRI $ix2, #0
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LRI $ix3, #0
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LRI $ax0.h, #positive_value
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LRI $ax1.h, #negative_value
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SR @positive_dmem_value_addr, $ax0.h
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SR @negative_dmem_value_addr, $ax1.h
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LRI $cr, #(positive_dmem_value_addr / 256)
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SET40
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; Instructions that perform sign-extension
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; $acc0 should alternate between being positive and negative here
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; (though none of these instructions update $sr)
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; [1] ILRR (also ILRRD/ILRRI/ILRRN, not covered)
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ILRR $ac0.m, @$ar2 ; -
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CALL send_back
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; [2] LR
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LR $ac0.m, @positive_dmem_value_addr ; +
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CALL send_back
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; [3] LRI
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LRI $ac0.m, #negative_value ; -
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CALL send_back
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; [4] LRIS
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LRIS $ac0.m, #42 ; +
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CALL send_back
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; [5] LRR (also LRRD/LRRI/LRRN)
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LRR $ac0.m, @$ar1 ; -
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CALL send_back
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; [6] LRS
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LRS $ac0.m, @(positive_dmem_value_addr & 0xff) ; +
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CALL send_back
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; [7] MRR
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MRR $ac0.m, $ax1.h ; -
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CALL send_back
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; [8] 'LN (and 'L, but 'LN lets us set $ix0 to not increment $ar0)
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NX'LN : $ac0.m, @$ar0 ; +
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CALL send_back
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; Instructions that experience saturation
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; $ax1.l should alternate between 0x8000 and 0x7fff.
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LRI $ac0.m, #0x4231
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LRI $ac0.h, #0x12 ; positive
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LRI $ac1.m, #0x2816
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LRI $ac1.h, #0x99 ; negative
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; [9] MRR (again)
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MRR $ax1.l, $ac1.m ; -
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CALL send_back
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; [10] SR
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SR @readback_dmem_addr, $ac0.m
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LR $ax1.l, @readback_dmem_addr ; +
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CALL send_back
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; [11] SRRN (also SRR/SRRD/SRRI)
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SRRN @$ar3, $ac1.m
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LR $ax1.l, @readback_dmem_addr ; -
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CALL send_back
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; [12] SRS
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SRS @(readback_dmem_addr & 0xff), $ac0.m
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LR $ax1.l, @readback_dmem_addr ; +
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CALL send_back
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; [13] 'LSNM (also 'LS/'LSM/'LSN) - the $ax0.l read is not relevant
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NX'LSNM : $ax0.l, $ac1.m
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LR $ax1.l, @readback_dmem_addr ; -
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CALL send_back
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; [14] 'MV
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NX'MV : $ax1.l, $ac0.m ; +
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CALL send_back
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; [15] 'SLNM (also 'SL/'SLM/'SLN) - the $ax0.l read is not relevant
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; Note that 'SL stores to @$ar0, while 'LS stores to @$ar3
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LRI $ar0, #readback_dmem_addr
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NX'SLNM : $ac1.m, $ax0.l
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LR $ax1.l, @readback_dmem_addr ; -
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CALL send_back
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LRI $ar0, #positive_dmem_value_addr
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; [16] 'SN (also 'S)
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NX'SN : @$ar3, $ac0.m
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LR $ax1.l, @readback_dmem_addr ; +
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CALL send_back
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; Instructions that are not affected
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; [17] ADDI
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ADDI $ac0.m, #8
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CALL send_back
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; [18] ADDIS
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ADDIS $ac0.m, #-8
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CALL send_back
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; [19] ANDC
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ANDC $ac1.m, $ac0.m
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CALL send_back
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; [20] ANDI
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ANDI $ac0.m, #0x6666
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CALL send_back
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; [21] ANDR
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ANDR $ac0.m, $ax0.h
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CALL send_back
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; [22] ORC
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ORC $ac0.m, $ac1.m
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CALL send_back
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; [23] ORI
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ORI $ac0.m, #0xfeed
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CALL send_back
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; [24] ORR
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ORR $ac1.m, $ax0.h
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CALL send_back
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; [25] NOT
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NOT $ac1.m
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CALL send_back
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; [26] XORC
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XORC $ac0.m, $ac1.m
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CALL send_back
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; [27] XORI
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XORI $ac0.m, #0x5555
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CALL send_back
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; [28] XORR
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XORR $ac1.m, $ax1.h
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CALL send_back
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; [29] MOVR always sign extends...
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MOVR $acc1, $ax0.h
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CALL send_back
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; [30] ... even in SET16 mode
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SET16
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MOVR $acc1, $ax1.h
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CALL send_back
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SET40
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; Shift instructions - do these see saturated $ac1.m?
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LRI $ac0.m, #positive_value
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LRI $ac1.m, #2
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LRI $ac1.h, #1
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; [31] - for diffs only
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CALL send_back
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; [32]
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LSRNR $acc0, $ac1.m
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CALL send_back
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; [33] Shifts $acc0 by $ac1.m (in the other direction)
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LSRN
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CALL send_back
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|
||||
; Does LOOP experience saturation?
|
||||
CLR $acc0
|
||||
LRI $ac1.m, #0x1234
|
||||
LRI $ac1.h, #1
|
||||
; [34] - for diffs only
|
||||
CALL send_back
|
||||
; [35] LOOP
|
||||
LOOP $ac1.m
|
||||
INC $acc0
|
||||
CALL send_back
|
||||
LRI $ac1.h, #0x99
|
||||
; [36] BLOOP
|
||||
BLOOP $ac1.m, bloop_last_ins
|
||||
INCM $ac0.m
|
||||
bloop_last_ins:
|
||||
NOP
|
||||
CALL send_back
|
||||
|
||||
; For the sake of clarity, the same LOOP/BLOOP calls in SET16 mode don't have saturation:
|
||||
SET16
|
||||
CLR $acc0
|
||||
LRI $ac1.m, #0x1234
|
||||
LRI $ac1.h, #1
|
||||
; [37] - for diffs only
|
||||
CALL send_back
|
||||
; [38] LOOP
|
||||
LOOP $ac1.m
|
||||
INC $acc0
|
||||
CALL send_back
|
||||
LRI $ac1.h, #0x99
|
||||
; [39] BLOOP
|
||||
BLOOP $ac1.m, bloop2_last_ins
|
||||
INCM $ac0.m
|
||||
bloop2_last_ins:
|
||||
NOP
|
||||
CALL send_back
|
||||
|
||||
; We're done, DO NOT DELETE THIS LINE
|
||||
JMP end_of_test
|
||||
164
Source/DSPSpy/tests/40bit_test.ds
Normal file
164
Source/DSPSpy/tests/40bit_test.ds
Normal file
@ -0,0 +1,164 @@
|
||||
; This test covers the behavior of 40-bit mode for a variety of values.
|
||||
; It takes a while to run completely (~5 minutes), but progress is indicated via mail shown at the
|
||||
; top of the screen in DSPSpy. The value will go from 80000000 to 8041ffff.
|
||||
incdir "tests"
|
||||
include "dsp_base.inc"
|
||||
|
||||
|
||||
|
||||
test_main:
|
||||
LRI $ar0, #0
|
||||
LRI $ar1, #0
|
||||
LRI $ar2, #0
|
||||
LRI $ar3, #0
|
||||
LRI $ix0, #0
|
||||
LRI $ix1, #0
|
||||
LRI $ix2, #0
|
||||
LRI $ix3, #0
|
||||
|
||||
; Test with $ac0.l from 0xfff0 to 0x0010
|
||||
LRI $ac0.l, #0xfff0
|
||||
BLOOPI #0x21, first_loop_last_ins
|
||||
CALL test_saturation
|
||||
IAR $ar0
|
||||
first_loop_last_ins:
|
||||
INC $acc0
|
||||
|
||||
; Test with $ac0.l from 0x7ff0 to 0x8010
|
||||
LRI $ac0.l, #0xfff0
|
||||
BLOOPI #0x21, second_loop_last_ins
|
||||
CALL test_saturation
|
||||
IAR $ar0
|
||||
second_loop_last_ins:
|
||||
INC $acc0
|
||||
|
||||
; We're done. Report the test results.
|
||||
; $ix1 should be 0, or else saturation occurred on $ac0.l or $ac0.h.
|
||||
; $ix2 should be 0, or else sign-extension occurred on $ac0.l or $ac0.h.
|
||||
; $ix3 should be 0, or else we incorrectly predicted saturation on $ac0.m.
|
||||
; $ar1/$ar2/$ar3 records the number of times it happened
|
||||
CALL send_back
|
||||
|
||||
; We're done, DO NOT DELETE THIS LINE
|
||||
JMP end_of_test
|
||||
|
||||
|
||||
|
||||
test_saturation:
|
||||
; We start with $ac0.h at -0x80 since we can use the overflow flag to check when wrapping around
|
||||
; occurs; starting at 0 and ending when it wraps back to 0 doesn't work since we can't check the
|
||||
; zero flag since $ac0.l may be nonzero ($ac0.l is used as an input to this subroutine)
|
||||
LRI $ac0.m, #0
|
||||
LRI $ac0.h, #-0x80
|
||||
|
||||
loop_start:
|
||||
; Compare the value of $ac0.m when in SET16 mode and in SET40 mode
|
||||
SET40
|
||||
; Reading $ac0.m in SET40 mode results in saturation if $ac0.h doesn't match the sign-extension
|
||||
; of $ac0.h. Also, storing to $ac1.m in SET40 mode clears $ac1.l and sets $ac1.h to the
|
||||
; sign-extension of $ac1.m, and $ac1.l.
|
||||
MRR $ac1.m, $ac0.m
|
||||
SET16
|
||||
; Attempt to compute the saturated value of $ac1.m in $ax1.h,
|
||||
; using what we know of $acc0.
|
||||
TST'MV $acc0 : $ax1.h, $ac0.m
|
||||
JL negative_acc0
|
||||
; $acc0 is nonnegative.
|
||||
JMPx8 check_saturated_ax1h ; If the above s32 bit is not set, we don't need to saturate
|
||||
; If the above s32 bit _is_ set, then saturate $ax1.h.
|
||||
LRI $ax1.h, #0x7fff
|
||||
JMP check_saturated_ax1h
|
||||
|
||||
negative_acc0:
|
||||
JMPx8 check_saturated_ax1h ; If the above s32 bit is not set, we don't need to saturate
|
||||
LRI $ax1.h, #0x8000
|
||||
; Fall through to check_saturated_ax1h
|
||||
|
||||
check_saturated_ax1h:
|
||||
; $acc1 has the value of $ac0.m in SET40 mode.
|
||||
; And, $ax1.h has what we computed that value should be, and CMPAXH always sign-extends $ax1.h
|
||||
; (and ignores $ax1.l), so we can compare using it directly.
|
||||
CMPAXH $acc1, $ax1.h
|
||||
JZ check_read_low
|
||||
; Our prediction was wrong (shouldn't happen)
|
||||
LRI $ix3, #1
|
||||
IAR $ar3
|
||||
TST $acc0
|
||||
CALL send_back
|
||||
; Fall through to check_read_low
|
||||
|
||||
check_read_low:
|
||||
SET40
|
||||
MRR $ac1.m, $ac0.l
|
||||
SET16
|
||||
MRR $ax1.h, $ac0.l
|
||||
CMPAXH $acc1, $ax1.h
|
||||
JZ check_read_high
|
||||
; Reading $ac0.l gave different results in SET40 and SET16 modes (shouldn't happen)
|
||||
LRI $ix1, #1
|
||||
IAR $ar1
|
||||
TST $acc0
|
||||
CALL send_back
|
||||
; Fall through to check_read_high
|
||||
|
||||
check_read_high:
|
||||
SET40
|
||||
MRR $ac1.m, $ac0.h
|
||||
SET16
|
||||
MRR $ax1.h, $ac0.h
|
||||
CMPAXH $acc1, $ax1.h
|
||||
JZ check_write_low
|
||||
; Reading $ac0.h gave different results in SET40 and SET16 modes (shouldn't happen)
|
||||
LRI $ix1, #1
|
||||
IAR $ar1
|
||||
TST $acc0
|
||||
CALL send_back
|
||||
; Fall through to check_write_low
|
||||
|
||||
check_write_low:
|
||||
MOV $acc1, $acc0
|
||||
SET40
|
||||
MRR $ac1.l, $ac0.l
|
||||
SET16
|
||||
CMP
|
||||
JZ check_write_high
|
||||
; Writing to $ac1.l caused $acc1 to not match $acc0 (shouldn't happen)
|
||||
LRI $ix2, #1
|
||||
IAR $ar2
|
||||
CALL send_back
|
||||
; Fall through to check_write_high
|
||||
|
||||
check_write_high:
|
||||
MOV $acc1, $acc0
|
||||
SET40
|
||||
MRR $ac1.h, $ac0.h
|
||||
SET16
|
||||
CMP
|
||||
JZ increment_loop
|
||||
; Writing to $ac1.h caused $acc1 to not match $acc0 (shouldn't happen)
|
||||
LRI $ix2, #1
|
||||
IAR $ar2
|
||||
CALL send_back
|
||||
; Fall through to increment_loop
|
||||
|
||||
increment_loop:
|
||||
INCM $ac0.m
|
||||
; If incrementing results in overflowing, then we're done.
|
||||
RETO
|
||||
|
||||
; If ($ac0.m & 0x00ff) != 0, continue the loop without sending mail.
|
||||
ANDF $ac0.m, #0x00ff
|
||||
JLNZ loop_start
|
||||
; Otherwise, send mail to report the progress. (This shows at the top of the screen in DSPSpy,
|
||||
; but otherwise isn't handled in any meaningful way.)
|
||||
MOV $acc1, $acc0
|
||||
LSR $acc1, #-8
|
||||
; Compensate for starting at INT_MIN (0x80'0000'0000) and ending at INT_MAX (0x7f'0000'0000)
|
||||
; instead of going from 0 (0x00'0000'0000) to -1 (0xff'ffff'ffff)
|
||||
XORI $ac1.m, #0x8000
|
||||
|
||||
SR @DMBH, $ar0
|
||||
SR @DMBL, $ac1.m
|
||||
SI @DIRQ, #0x0001
|
||||
; We don't wait for the mail to be read, because we don't care about the response.
|
||||
JMP loop_start
|
||||
Reference in New Issue
Block a user