piwalker/dolphin
1
0
Fork 0
mirror of https://github.com/dolphin-emu/dolphin.git synced 2025-07-25 15:19:42 -06:00
Code Issues Packages Projects Releases Wiki Activity

some HLE LLE stuff :)

Browse Source 
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@837 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
fires.gc
2008-10-11 08:43:50 +00:00
parent 4d93e126de
commit f9bd977ffd
15 changed files with 146 additions and 66 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
Docs/DSP/DSP_InterC/DSP_InterC/DSPExt.cpp
View File

@ -79,7 +79,7 @@ void dsp_op_ext_s(uint16 _Opcode)
uint8 dreg = _Opcode & 0x3;
uint8 sreg = ((_Opcode >> 3) & 0x3) + 0x1c;
OutBuffer::AddCode("*(%s) = %s", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(sreg));
OutBuffer::AddCode("WriteDMEM(%s, %s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(sreg));
// dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
if (_Opcode & 0x04)
@ -100,7 +100,7 @@ void dsp_op_ext_l(uint16 _Opcode)
uint8 sreg = _Opcode & 0x3;
uint8 dreg = ((_Opcode >> 3) & 0x7) + 0x18;
OutBuffer::AddCode("%s = *(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(sreg));
OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(sreg));
// uint16 val = dsp_dmem_read(g_dsp.r[sreg]);
// g_dsp.r[dreg] = val;
@ -121,7 +121,7 @@ void dsp_op_ext_ls_pro(uint16 _Opcode)
{
uint8 areg = (_Opcode & 0x1) + 0x1e;
OutBuffer::AddCode("*(%s) = %s", OutBuffer::GetRegName(0x03), OutBuffer::GetRegName(areg));
OutBuffer::AddCode("WriteDMEM(%s, %s)", OutBuffer::GetRegName(0x03), OutBuffer::GetRegName(areg));
// dsp_dmem_write(g_dsp.r[0x03], g_dsp.r[areg]);
if (_Opcode & 0x8)
@ -141,7 +141,7 @@ void dsp_op_ext_ls_epi(uint16 _Opcode)
{
uint8 dreg = ((_Opcode >> 4) & 0x3) + 0x18;
OutBuffer::AddCode("%s = *(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(0x00));
OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(0x00));
// uint16 val = dsp_dmem_read(g_dsp.r[0x00]);
// dsp_op_write_reg(dreg, val);
@ -162,7 +162,7 @@ void dsp_op_ext_sl_pro(uint16 _Opcode)
{
uint8 areg = (_Opcode & 0x1) + 0x1e;
OutBuffer::AddCode("*(%s) = %s", OutBuffer::GetRegName(0x00), OutBuffer::GetRegName(areg));
OutBuffer::AddCode("WriteDMEM(%s, %s)", OutBuffer::GetRegName(0x00), OutBuffer::GetRegName(areg));
// dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
if (_Opcode & 0x4)
@ -182,7 +182,7 @@ void dsp_op_ext_sl_epi(uint16 _Opcode)
{
uint8 dreg = ((_Opcode >> 4) & 0x3) + 0x18;
OutBuffer::AddCode("%s = *(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(0x03));
OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(0x03));
// uint16 val = dsp_dmem_read(g_dsp.r[0x03]);
// dsp_op_write_reg(dreg, val);
@ -205,8 +205,8 @@ void dsp_op_ext_ld(uint16 _Opcode)
uint8 dreg2 = (((_Opcode >> 4) & 0x1) << 1) + 0x19;
uint8 sreg = _Opcode & 0x3;
OutBuffer::AddCode("%s = *(%s)", OutBuffer::GetRegName(dreg1), OutBuffer::GetRegName(sreg));
OutBuffer::AddCode("%s = *(%s)", OutBuffer::GetRegName(dreg2), OutBuffer::GetRegName(0x03));
OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg1), OutBuffer::GetRegName(sreg));
OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg2), OutBuffer::GetRegName(0x03));
// g_dsp.r[dreg1] = dsp_dmem_read(g_dsp.r[sreg]);
// g_dsp.r[dreg2] = dsp_dmem_read(g_dsp.r[0x03]);

10
Docs/DSP/DSP_InterC/DSP_InterC/DSPOpcodes.cpp
View File

@ -318,7 +318,7 @@ void dsp_opc_lrr(uint16 opc)
uint8 sreg = (opc >> 5) & 0x3;
uint8 dreg = opc & 0x1f;
OutBuffer::AddCode("%s = *(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(sreg));
OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(sreg));
// uint16 val = dsp_dmem_read(g_dsp.r[sreg]);
// dsp_op_write_reg(dreg, val);
@ -352,7 +352,7 @@ void dsp_opc_srr(uint16 opc)
uint8 dreg = (opc >> 5) & 0x3;
uint8 sreg = opc & 0x1f;
OutBuffer::AddCode("*(%s) = %s", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(sreg));
OutBuffer::AddCode("WriteDMEM(%s, %s)", OutBuffer::GetRegName(dreg), OutBuffer::GetRegName(sreg));
//uint16 val = dsp_op_read_reg(sreg);
// dsp_dmem_write(g_dsp.r[dreg], val);
@ -1177,7 +1177,7 @@ void dsp_opc_asr16(uint16 opc)
uint8 areg = (opc >> 11) & 0x1;
OutBuffer::AddCode("ACC%i >>= 16", areg);
OutBuffer::AddCode("Update_SR_Register(AC%i)", areg);
OutBuffer::AddCode("Update_SR_Register(ACC%i)", areg);
//sint64 acc = dsp_get_long_acc(areg);
//acc >>= 16;
@ -1885,14 +1885,14 @@ void dsp_op2(uint16 opc)
if (opc & 0x0800)
{
OutBuffer::AddCode("*(%s) = %s", OutBuffer::GetMemName(addr), OutBuffer::GetRegName(reg));
OutBuffer::AddCode("WriteDMEM(%s, %s)", OutBuffer::GetMemName(addr), OutBuffer::GetRegName(reg));
// srs
// dsp_dmem_write(addr, g_dsp.r[reg]);
}
else
{
OutBuffer::AddCode("%s = *(%s)", OutBuffer::GetRegName(reg), OutBuffer::GetMemName(addr));
OutBuffer::AddCode("%s = ReadDMEM(%s)", OutBuffer::GetRegName(reg), OutBuffer::GetMemName(addr));
// lrs
// g_dsp.r[reg] = dsp_dmem_read(addr);

2
Docs/DSP/DSP_InterC/DSP_InterC/DSP_InterC.cpp
View File

@ -26,7 +26,7 @@ void Decode(uint16 startAddress, uint16 endAddress)
uint16 oldPC = g_currentAddress;
uint16 op = FetchOpcode();
OutBuffer::Add("%4X:", oldPC);
OutBuffer::Add("l_%4X:", oldPC);
DecodeOpcode(op);
}
}

26
Docs/DSP/DSP_InterC/DSP_InterC/OutBuffer.cpp
View File

@ -35,7 +35,7 @@ namespace OutBuffer
vsprintf(Msg, _fmt, ap);
va_end(ap);
printf(" %s\n", Msg);
printf(" %s;\n", Msg);
}
// predefined labels
@ -68,18 +68,18 @@ namespace OutBuffer
{0x11, "ACH1", "Accumulator High 1",},
{0x12, "CR", "Config Register",},
{0x13, "SR", "Special Register",},
{0x14, "PROD.L", "PROD L",},
{0x15, "PROD.M1", "PROD M1",},
{0x16, "PROD.H", "PROD H",},
{0x17, "PROD.M2", "PROD M2",},
{0x18, "AX0.L", "Additional Accumulators Low 0",},
{0x19, "AX1.L", "Additional Accumulators Low 1",},
{0x1a, "AX0.H", "Additional Accumulators High 0",},
{0x1b, "AX1.H", "Additional Accumulators High 1",},
{0x1c, "AC0.L", "Register 28",},
{0x1d, "AC1.L", "Register 29",},
{0x1e, "AC0.M", "Register 00",},
{0x1f, "AC1.M", "Register 00",},
{0x14, "PROD_l", "PROD L",},
{0x15, "PROD_m1", "PROD M1",},
{0x16, "PROD_h", "PROD H",},
{0x17, "PROD_m2", "PROD M2",},
{0x18, "AX0_l", "Additional Accumulators Low 0",},
{0x19, "AX1_l", "Additional Accumulators Low 1",},
{0x1a, "AX0_h", "Additional Accumulators High 0",},
{0x1b, "AX1_h", "Additional Accumulators High 1",},
{0x1c, "AC0_l", "Register 28",},
{0x1d, "AC1_l", "Register 29",},
{0x1e, "AC0_m", "Register 00",},
{0x1f, "AC1_m", "Register 00",},
// additional to resolve special names
{0x20, "ACC0", "Accumulators 0",},