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Merge pull request #5159 from ligfx/arm64warnings

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Arm64: a slew of warning fixes
This commit is contained in:
Markus Wick
2017-04-02 17:07:17 +02:00
committed by GitHub
parent 40cfa708a8 9afe3946d1
commit fd7f7c5541
4 changed files with 77 additions and 54 deletions
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3
Source/Core/Core/PowerPC/JitArm64/JitArm64_BackPatch.cpp
View File

@ -2,6 +2,7 @@
// Licensed under GPLv2+
// Refer to the license.txt file included.
#include <cinttypes>
#include <string>
#include "Common/BitSet.h"
@ -38,7 +39,7 @@ void JitArm64::DoBacktrace(uintptr_t access_address, SContext* ctx)
Common::swap32(*(u32*)(pc + 4)), Common::swap32(*(u32*)(pc + 8)),
Common::swap32(*(u32*)(pc + 12)));
ERROR_LOG(DYNA_REC, "0x%016lx: %08x %08x %08x %08x", pc, *(u32*)pc, *(u32*)(pc + 4),
ERROR_LOG(DYNA_REC, "0x%016" PRIx64 ": %08x %08x %08x %08x", pc, *(u32*)pc, *(u32*)(pc + 4),
*(u32*)(pc + 8), *(u32*)(pc + 12));
}

31
Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
View File

@ -115,6 +115,21 @@ void JitArm64::reg_imm(u32 d, u32 a, u32 value, u32 (*do_op)(u32, u32),
}
}
static constexpr u32 BitOR(u32 a, u32 b)
{
return a | b;
}
static constexpr u32 BitAND(u32 a, u32 b)
{
return a & b;
}
static constexpr u32 BitXOR(u32 a, u32 b)
{
return a ^ b;
}
void JitArm64::arith_imm(UGeckoInstruction inst)
{
INSTRUCTION_START
@ -129,23 +144,22 @@ void JitArm64::arith_imm(UGeckoInstruction inst)
// NOP
return;
}
reg_imm(a, s, inst.UIMM, [](u32 a, u32 b) { return a | b; }, &ARM64XEmitter::ORRI2R);
reg_imm(a, s, inst.UIMM, BitOR, &ARM64XEmitter::ORRI2R);
break;
case 25: // oris
reg_imm(a, s, inst.UIMM << 16, [](u32 a, u32 b) { return a | b; }, &ARM64XEmitter::ORRI2R);
reg_imm(a, s, inst.UIMM << 16, BitOR, &ARM64XEmitter::ORRI2R);
break;
case 28: // andi
reg_imm(a, s, inst.UIMM, [](u32 a, u32 b) { return a & b; }, &ARM64XEmitter::ANDI2R, true);
reg_imm(a, s, inst.UIMM, BitAND, &ARM64XEmitter::ANDI2R, true);
break;
case 29: // andis
reg_imm(a, s, inst.UIMM << 16, [](u32 a, u32 b) { return a & b; }, &ARM64XEmitter::ANDI2R,
true);
reg_imm(a, s, inst.UIMM << 16, BitAND, &ARM64XEmitter::ANDI2R, true);
break;
case 26: // xori
reg_imm(a, s, inst.UIMM, [](u32 a, u32 b) { return a ^ b; }, &ARM64XEmitter::EORI2R);
reg_imm(a, s, inst.UIMM, BitXOR, &ARM64XEmitter::EORI2R);
break;
case 27: // xoris
reg_imm(a, s, inst.UIMM << 16, [](u32 a, u32 b) { return a ^ b; }, &ARM64XEmitter::EORI2R);
reg_imm(a, s, inst.UIMM << 16, BitXOR, &ARM64XEmitter::EORI2R);
break;
}
}
@ -161,7 +175,6 @@ void JitArm64::addix(UGeckoInstruction inst)
{
imm <<= 16;
}
u32 imm_neg = 0u - imm;
if (a)
{
@ -1136,7 +1149,7 @@ void JitArm64::divwx(UGeckoInstruction inst)
if (inst.Rc)
ComputeRC(imm_d);
}
else if (gpr.IsImm(b) && gpr.GetImm(b) != 0 && gpr.GetImm(b) != -1)
else if (gpr.IsImm(b) && gpr.GetImm(b) != 0 && gpr.GetImm(b) != -1u)
{
ARM64Reg WA = gpr.GetReg();
MOVI2R(WA, gpr.GetImm(b));