piwalker/dolphin
1
0
Fork 0
mirror of https://github.com/dolphin-emu/dolphin.git synced 2024-11-15 05:47:56 -07:00
Code Issues Actions Packages Projects Releases Wiki Activity

Merge pull request #3195 from lioncash/android

Browse Source 
Arm64Emitter: Minor changes
This commit is contained in:
Lioncash 2015-10-24 12:06:53 -04:00
commit fe10a20be1
2 changed files with 26 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
Source/Core/Common/Arm64Emitter.cpp
View File

@ -3,6 +3,7 @@
// Refer to the license.txt file included. // Refer to the license.txt file included.
#include <algorithm> #include <algorithm>
#include <cstring>
#include <vector> #include <vector>
#include "Common/Arm64Emitter.h" #include "Common/Arm64Emitter.h"
@ -312,6 +313,12 @@ const u8* ARM64XEmitter::AlignCodePage()
return m_code; return m_code;
} }
void ARM64XEmitter::Write32(u32 value)
{
std::memcpy(m_code, &value, sizeof(u32));
m_code += sizeof(u32);
}
void ARM64XEmitter::FlushIcache() void ARM64XEmitter::FlushIcache()
{ {
FlushIcacheSection(m_lastCacheFlushEnd, m_code); FlushIcacheSection(m_lastCacheFlushEnd, m_code);
@ -815,32 +822,32 @@ void ARM64XEmitter::EncodeLoadStoreUnscaled(u32 size, u32 op, ARM64Reg Rt, ARM64
Write32((size << 30) | (0b111 << 27) | (op << 22) | ((imm & 0x1FF) << 12) | (Rn << 5) | Rt); Write32((size << 30) | (0b111 << 27) | (op << 22) | ((imm & 0x1FF) << 12) | (Rn << 5) | Rt);
} }
static inline bool IsInRangeImm19(s64 distance) static constexpr bool IsInRangeImm19(s64 distance)
{ {
return (distance >= -0x40000 && distance <= 0x3FFFF); return (distance >= -0x40000 && distance <= 0x3FFFF);
} }
static inline bool IsInRangeImm14(s64 distance) static constexpr bool IsInRangeImm14(s64 distance)
{ {
return (distance >= -0x2000 && distance <= 0x1FFF); return (distance >= -0x2000 && distance <= 0x1FFF);
} }
static inline bool IsInRangeImm26(s64 distance) static constexpr bool IsInRangeImm26(s64 distance)
{ {
return (distance >= -0x2000000 && distance <= 0x1FFFFFF); return (distance >= -0x2000000 && distance <= 0x1FFFFFF);
} }
static inline u32 MaskImm19(s64 distance) static constexpr u32 MaskImm19(s64 distance)
{ {
return distance & 0x7FFFF; return distance & 0x7FFFF;
} }
static inline u32 MaskImm14(s64 distance) static constexpr u32 MaskImm14(s64 distance)
{ {
return distance & 0x3FFF; return distance & 0x3FFF;
} }
static inline u32 MaskImm26(s64 distance) static constexpr u32 MaskImm26(s64 distance)
{ {
return distance & 0x3FFFFFF; return distance & 0x3FFFFFF;
} }

30
Source/Core/Common/Arm64Emitter.h
View File

@ -81,19 +81,19 @@ enum ARM64Reg
INVALID_REG = 0xFFFFFFFF INVALID_REG = 0xFFFFFFFF
}; };
inline bool Is64Bit(ARM64Reg reg) { return (reg & 0x20) != 0; } constexpr bool Is64Bit(ARM64Reg reg) { return (reg & 0x20) != 0; }
inline bool IsSingle(ARM64Reg reg) { return (reg & 0xC0) == 0x40; } constexpr bool IsSingle(ARM64Reg reg) { return (reg & 0xC0) == 0x40; }
inline bool IsDouble(ARM64Reg reg) { return (reg & 0xC0) == 0x80; } constexpr bool IsDouble(ARM64Reg reg) { return (reg & 0xC0) == 0x80; }
inline bool IsScalar(ARM64Reg reg) { return IsSingle(reg) || IsDouble(reg); } constexpr bool IsScalar(ARM64Reg reg) { return IsSingle(reg) || IsDouble(reg); }
inline bool IsQuad(ARM64Reg reg) { return (reg & 0xC0) == 0xC0; } constexpr bool IsQuad(ARM64Reg reg) { return (reg & 0xC0) == 0xC0; }
inline bool IsVector(ARM64Reg reg) { return (reg & 0xC0) != 0; } constexpr bool IsVector(ARM64Reg reg) { return (reg & 0xC0) != 0; }
inline bool IsGPR(ARM64Reg reg) { return (int)reg < 0x40; } constexpr bool IsGPR(ARM64Reg reg) { return static_cast<int>(reg) < 0x40; }
inline ARM64Reg DecodeReg(ARM64Reg reg) { return (ARM64Reg)(reg & 0x1F); } constexpr ARM64Reg DecodeReg(ARM64Reg reg) { return static_cast<ARM64Reg>(reg & 0x1F); }
inline ARM64Reg EncodeRegTo64(ARM64Reg reg) { return (ARM64Reg)(reg | 0x20); } constexpr ARM64Reg EncodeRegTo64(ARM64Reg reg) { return static_cast<ARM64Reg>(reg | 0x20); }
inline ARM64Reg EncodeRegToSingle(ARM64Reg reg) { return (ARM64Reg)(DecodeReg(reg) + S0); } constexpr ARM64Reg EncodeRegToSingle(ARM64Reg reg) { return static_cast<ARM64Reg>(DecodeReg(reg) + S0); }
inline ARM64Reg EncodeRegToDouble(ARM64Reg reg) { return (ARM64Reg)((reg & ~0xC0) | 0x80); } constexpr ARM64Reg EncodeRegToDouble(ARM64Reg reg) { return static_cast<ARM64Reg>((reg & ~0xC0) | 0x80); }
inline ARM64Reg EncodeRegToQuad(ARM64Reg reg) { return (ARM64Reg)(reg | 0xC0); } constexpr ARM64Reg EncodeRegToQuad(ARM64Reg reg) { return static_cast<ARM64Reg>(reg | 0xC0); }
// For AND/TST/ORR/EOR etc // For AND/TST/ORR/EOR etc
bool IsImmLogical(uint64_t value, unsigned int width, unsigned int *n, unsigned int *imm_s, unsigned int *imm_r); bool IsImmLogical(uint64_t value, unsigned int width, unsigned int *n, unsigned int *imm_s, unsigned int *imm_r);
@ -359,11 +359,7 @@ private:
void EncodeLoadStoreUnscaled(u32 size, u32 op, ARM64Reg Rt, ARM64Reg Rn, s32 imm); void EncodeLoadStoreUnscaled(u32 size, u32 op, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
protected: protected:
inline void Write32(u32 value) void Write32(u32 value);
{
*(u32*)m_code = value;
m_code += 4;
}
public: public:
ARM64XEmitter() ARM64XEmitter()