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58 Commits

Author SHA1 Message Date
Lioncash
208be26bb4 Arm64Emitter: Make the Align* functions return a non-const data pointer 
Similar in nature to e28d063539 in which
this same change was applied to the x64 emitter.

There's no real requirement to make this const, and this should also
be decided by the calling code, considering we had places that would
simply cast away the const and carry on
 2018-08-27 09:44:38 -04:00
Lioncash
1c63a48fab Common/CodeBlock: Namespace code under the Common namespace 
Brings more common code under the Common namespace.
 2018-05-17 15:57:29 -04:00
Lioncash
91cefe6c8a
Arm64Emitter: Make IsImmArithmetic, IsImmLogical, FPImm8ToFloat, and FPImm8FromFloat internally linked 
These aren't used anywhere outside of the emitter. Centralizes them under an anonymous namespace.
 2018-03-23 19:17:26 -04:00
Lioncash
50a476c371 Assert: Uppercase assertion macros 
Macros should be all upper-cased. This is also kind of a wart that's
been sticking out for quite a while now (we avoid prefixing
underscores).
 2018-03-14 22:03:12 -04:00
degasus
304e601ad3 JitArm64: Reimplement aarch64 cycle counters. 
CNTVCT_EL0 is force-enabled on all linux plattforms.
Windows is untested, but as this is the best way to get *any* low
overhead performance counters, they likely use it as well.
 2017-09-02 13:24:37 +02:00
Markus Wick
d78009877b JitArm64: Fix LSL/LSR/ROR/ASR wrappers. 
The other method has a latency of 2 cycles. This also improves the
throughput a lot.
 2017-08-12 00:00:41 +02:00
Tillmann Karras
c54c49714d Arm64Emitter: add FRECPE 2017-05-03 08:02:35 +01:00
Michael Maltese
3d7bace9da Arm64Emitter: extract lambda to AddImmediate() 
Fixes warning:

```
Source/Core/Common/Arm64Emitter.cpp:4108:31: error: declaration shadows a local variable [-Werror,-Wshadow]
    auto addi = [this](ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool shift, bool negative, bool flags) {
                                ^
  /var/lib/buildbot/slave/pr-android/build/Source/Core/Common/Arm64Emitter.cpp:4105:46: note: previous declaration is here
  void ARM64XEmitter::ADDI2R_internal(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool negative, bool flags,
                                               ^
```
 2017-03-25 14:21:19 -07:00
Lioncash
a7ec2d3831 Arm64Emitter: Get rid of pointer casts in PoisonMemory 
The previous code invokes undefined behavior.
 2017-03-23 07:10:21 -04:00
degasus
f1a67bb1a2 JitArm64: Implement divwx 2016-10-29 13:35:23 +02:00
degasus
8ad98d0046 ArmEmitter: Merge AddI2R helpers. 2016-10-27 19:19:06 +02:00
degasus
694e9b4132 JitArm64: ADDI2R optimizations 2. 2016-10-27 19:19:06 +02:00
degasus
df250b84cc JitArm64: Avoid MOVI2R is possible. 
Just use all kind of ADDI2R, SUBI2R, ...
They have some optimizations internally.
 2016-10-26 21:54:09 +02:00
Pierre Bourdon
3570c7f03a Reformat all the things. Have fun with merge conflicts. 2016-06-24 10:43:46 +02:00
degasus
9ed465f4ac JitArm64: Implement mulhwx 2016-03-04 22:51:46 +01:00
mathieui
4b06e92731 A few more asterisks, mostly casts 2016-01-21 22:20:22 +01:00
mathieui
3e283ea9f1 More asterisks 2016-01-21 21:16:51 +01:00
mathieui
78aa398e7c Common: asterisks go against the type name 
not the variable name
 2016-01-21 20:46:25 +01:00
Lioncash
2630752ffe Arm64Emitter: Get rid of a pointer cast 2015-10-22 15:32:11 -04:00
Lioncash
018c85c248 Arm64Emitter: Mark trivial functions as constexpr 2015-10-22 15:22:38 -04:00
Lioncash
19ac565e0d Common: Move asserts to their own header 2015-09-26 18:51:27 -04:00
Ryan Houdek
d495ad5104 [AArch64] Make TST reg, reg emitter alias 2015-08-31 14:03:32 -05:00
Ryan Houdek
b907576510 [AArch64] Support profiling by cycle counters if they are available to EL0 2015-08-30 10:25:16 -05:00
Ryan Houdek
4fa23abbe1 [AArch64] Implement MOVI and ORR(imm) in the NEON emitter. 2015-08-23 15:34:53 -05:00
degasus
9bfff0d461 JitArm64: Fix jit clearing 
We have to reset m_lastCacheFlushEnd on clearing.
 2015-08-15 11:41:01 +02:00
degasus
b8dd68beef JitArm64: Far Code Cache 2015-07-12 09:41:32 +02:00
Jeffrey Pfau
c9a25f9484 Common: CallLambdaTrampoline can return a value 
As it is currently written, CallLambdaTrampoline does not return a
value. However, some of the functions that are being wrapped may
return a value that the JIT is expected to understand. A compiler
*cough cough clang* may opt to alter %rax after the wrapped lambda
returns, e.g. popping a previous value, which can clobber the
return value. If we actually have a return value, then the compiler
must not clobber it.
 2015-07-04 00:57:41 -07:00
Ryan Houdek
afc3d30f5c [AArch64] Implement BFI & UBFIZ in the emitter. 
Also fixes a bug in the UBFX instruction emitter. Naughty Naughty PPSSPP, not testing emitter functions you add.
 2015-06-29 19:00:22 -05:00
Ryan Houdek
5dc148159f [AArch64] Implement {U, S}QXTN{,2} 
Also split out XTN to XTN and XTN2.
 2015-06-13 23:16:17 -05:00
Ryan Houdek
3d2b116323 [AArch64] Implement a couple instructions in the emitter. 
Implements LD2R.
Implements LD1R/LD2R with post-indexing support.
Implements vector min/max instructions.
 2015-06-09 18:10:56 -05:00
Ryan Houdek
8ae12d8005 [AArch64] Add ASIMD LDR/STR with register offset 2015-06-07 19:53:05 -05:00
Ryan Houdek
05b72c5d31 [AArch64] Upstream PPSSPP's emitter changes. 
Requires a minor change to in the JIT to make sure everything still works.
 2015-06-07 19:50:21 -05:00
Lioncash
4f276ede0f Arm64Emitter: Make GetReg() const 2015-06-04 20:43:22 -04:00
Tillmann Karras
30ebb2459e Set copyright year to when a file was created 2015-05-25 13:22:31 +02:00
Tillmann Karras
cefcb0ace9 Update license headers to GPLv2+ 2015-05-25 13:22:31 +02:00
Ryan Houdek
f1a9db9bdc [AArch64] Stop violating the AAPCS64 so much. 2015-03-02 11:21:15 -06:00
Ryan Houdek
39e357d62d [AArch64] Implement VFP loadstore paired in the emitter. 2015-03-02 06:27:17 -06:00
Ryan Houdek
8b8310d28c [AArch64] Optimize FPR pushing and popping. 
Previously on FPR pushing and popping we would do a single STR/LDR per quad FPR we wanted to push/pop.
In most of our cases when we are pushing and popping VFP registers they will be consecutive registers that will save more efficiently using the NEON
loadstores that can do up to four quad registers.
So this can potentially cutting instructions down to ~1/4th the amount of instructions if the registers are all consecutive.

On the Cortex-A57 this is basically just an icache improvement, but on the Nvidia Denver this may be optimized to be more efficient. Either way it's a
win.
 2015-03-02 06:27:13 -06:00
Ryan Houdek
120df4c688 [AArch64] Implement loadstore unscaled. 2015-02-16 22:00:43 -06:00
Ryan Houdek
814aaaf538 [AArch64] Implement a couple of emitter instructions. 
These will be used with the vertex loader JIT recompiler.
 2015-02-13 12:16:06 -06:00
Ryan Houdek
0252bbb33f [AArch64] Fix non-PCH build. 2015-02-13 12:16:05 -06:00
Ryan Houdek
8074d06270 [ARM] Fix poison memory functions. 
We were poisoning 4x more data and overrunning our buffers. We don't want to do this.
 2015-02-13 12:16:05 -06:00
Ryan Houdek
8c53b88cc3 [AArch64] Implement a way to call lambdas in the emitter 2015-01-29 01:50:11 -06:00
Ryan Houdek
6470227a39 [AArch64] Minor fix in the UMULH/SMULH. 
These two instructions ignore the register encoded in to RA.
 2015-01-22 18:08:49 -06:00
Ryan Houdek
217c2c9d6a [AArch64] Add some more scalar VFP ops to the emitter. 2015-01-20 16:34:32 -06:00
Ryan Houdek
8d5947efac [AArch64] Emitter improvements. 
Adds a bunch of new instructions to the emitter.
 2015-01-18 16:25:40 -06:00
Ryan Houdek
c511ee763a [AArch64] Add the float emitter. 2015-01-08 19:55:31 -06:00
Ryan Houdek
5a0133c478 [AArch64] Add a few more VFP register helpers. 
Renames Is128Bit to IsQuad to line up more with the other helpers.
 2015-01-07 13:05:55 -06:00
Ryan Houdek
2b4f1aed40 [AArch64] Minor shifted register adjustment. 
If we have a shift amount that is the full length of the source register then we have an invalid instruction.
This can happen when dealing with a couple of PowerPC instructions.
This same adjustment is already in the ARMv7 emitter.
 2015-01-07 13:03:51 -06:00
Ryan Houdek
0a23ca9461 [AArch64] Add MUL/MNEG instruction aliases to the emitter. 2015-01-07 13:03:01 -06:00