Commit Graph

59 Commits

Author SHA1 Message Date
0a23ca9461 [AArch64] Add MUL/MNEG instruction aliases to the emitter. 2015-01-07 13:03:01 -06:00
8dba84dd7c [AArch64] Fix 8 & 16 bit loadstore indexes.
I wasn't bit shifting correctly for 8 and 16bit loadstores.
2015-01-07 12:58:37 -06:00
d3c2e8fb0a [AArch64] Improvements to the AArch64 emitter.
Fixes issues with negative offsets in loadstore instructions.
Adds ADRP/ADR instructions.
Optimizes MOVI2R function to take advantage of ADRP on pointers, can change a 3 instruction operation down to one.
Adds GPR push/pop operations for ABI related things.
2014-12-20 19:35:52 -06:00
2c39d4044d [AArch64] Add loadstore paired emitter instructions. 2014-12-02 21:08:34 -06:00
7608e3f11e Add AArch64 emitter aliases for MOV and MVN. 2014-09-18 16:30:40 -05:00
a92003c1ab ARM64: Make getters within ArithOption const. 2014-09-12 20:55:26 -04:00
24f6c98a55 Add sign extending aliases to the ARM64Emitter. 2014-09-10 17:52:54 -05:00
bc331ee809 Common: Fix code styling in Arm64Emitter 2014-09-08 23:39:20 -04:00
f107b5e176 [AArch64-emitter] Initial work on a emitter for 64bit ARM.
I've tested a few instruction encodings and am expecting most to work as long as one stays away from VFP/SIMD.
This implements mostly instructions to bring up an initial JIT with integer support.
This can be improved to allow ease of use functions in the future, dealing with the raw imms/immr encodings is probably the worst thing ever.
2014-09-06 20:13:44 -05:00