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126 Commits

Author SHA1 Message Date
Tillmann Karras
c2c31086ae XEmitter: restructure WriteVEXOp wrappers 2015-05-17 18:44:56 +02:00
Tillmann Karras
ae8efaa6a3 XEmitter: add VBLENDVPD and VCMPPD 2015-05-17 18:42:36 +02:00
Tillmann Karras
18e9241637 XEmitter: rename WriteVex to WriteVEX 2015-05-17 09:35:53 +02:00
Tillmann Karras
9e3f4df733 XEmitter: rename WriteRex to WriteREX 2015-05-17 09:35:53 +02:00
comex
b3aaa46d42 Merge pull request #2088 from Sintendo/diecmp 
Emit 'TEST reg, reg' for 'CMP reg, 0' automatically
 2015-04-23 16:34:23 -04:00
comex
ad95454d04 Merge pull request #2223 from phire/imm 
Cleanup OpArg, make immediates more explicit.
 2015-04-23 01:53:18 -04:00
Sintendo
c19482c9a3 Add function to emit CMP, or TEST when possible 
Also, a spelling mistake.
 2015-03-22 17:22:27 +01:00
magumagu
52aeab3d0e Merge pull request #2240 from lioncash/emitter 
x64Emitter: Remove emitter pointer parameter from WriteNormalOp.
 2015-03-20 22:09:11 -07:00
Lioncash
fab7add718 x64Emitter: Remove emitter pointer parameter from WriteNormalOp. 
It only ever passed the equivalent of the class' this pointer. May as well get rid of it.
 2015-03-20 23:28:36 -04:00
Tillmann Karras
9793fed742 XEmitter: add PUNPCKLQDQ 2015-03-18 12:09:06 +01:00
Scott Mansell
858ff69c01 Make OpArg.offset and operandReg private. 
Also cleaned up WriteRest function.
 2015-03-17 18:49:30 +13:00
Ryan Houdek
80e6367e46 Merge pull request #1869 from Stevoisiak/GeneralConsistency 
Minor consistency changes
 2015-01-21 13:46:53 -06:00
Tillmann Karras
e80b657cf4 Move MOVBE wrappers directly into XEmitter class 2015-01-18 13:29:34 +01:00
Tillmann Karras
eb13aa43fe XEmitter: overload MOVBE() 2015-01-18 12:59:33 +01:00
Stevoisiak
cb86db7b68 Minor consistency changes 
Mostly small changes, like capitalization and spelling
 2015-01-12 15:18:18 -05:00
Tillmann Karras
1efa9b8b72 x64Emitter: add MOVLPS/MOVHPS 2015-01-07 11:23:52 +01:00
Tillmann Karras
3daa6ab259 x64Emitter: fix MOVLPD/MOVHPD 
These instructions were using the wrong prefix which turned
MOVLPD(reg, mem) into MOVDDUP(reg, mem) and made the rest of them
invalid.
 2015-01-07 11:23:52 +01:00
Tillmann Karras
986d19b9d5 x64Emitter: fix bitwise AVX opcodes 
The reason this didn't break is that bitwise instructions like VPAND,
VANDPS, and VANDPD do the exact same thing. The only difference is the
data type they are intended for.
 2014-12-06 22:28:03 +01:00
Stevoisiak
b25e1a2eb4 Various formatting and consistency fixes 2014-11-13 22:42:18 -05:00
Fiora
6603f98d04 JIT: add 64-bit write support to FIFO functions 
Also fix 64-bit values passed to CallAC and otherwise correct immediate
handling in FIFO writes.
Fixes 007 Nightfire.
 2014-11-09 21:24:30 -08:00
skidau
9ddbdeb39f Merge pull request #995 from FioraAeterna/fma 
Add FMA support to emitter and use it in the JIT
 2014-10-12 13:56:18 +11:00
Henrik Rydgård
877081c7df Be consistent with braces. 2014-10-10 22:34:03 +02:00
Henrik Rydgård
9bca1a00d7 x64 emitter: Add some more missing ops (MOVDQA, MOVDQU, PSHUFHW) 
Also constify some pointers.
 2014-10-10 18:30:05 +02:00
Henrik Rydgård
a2c46665c5 x64 emitter: Add a few missing instructions 2014-10-10 18:30:04 +02:00
Fiora
019657cd93 X64Emitter: add FMA3 support 2014-10-07 18:21:07 -07:00
Fiora
7a2dd3a3c6 x64Emitter: refactor, add some new AVX instructions 2014-10-03 10:05:10 -07:00
Fiora
ac1fc9ad03 JIT+Emitter: support locking flags 
This helps us avoid accidentally clobbering flags between two instructions
when the flags are expected to be maintained. Dolphin will of course crash
immediately, but at least it will crash loudly and alert us of the mistake,
instead of forcing hours of bisecting to find the subtle way in which the JIT
has managed to sneak a flag-modifying instruction where there shouldn't be one.
 2014-09-26 20:47:06 -07:00
Fiora
3c49200b22 X64Emitter: add MOVHLPS/MOVLHPS 2014-09-18 17:57:27 -07:00
comex
7ad9027593 Be pedantic about stack overflow on Linux and OS X. 
Add some magic to the fault handler to handle stack overflow due to BLR
optimization, and disable the optimization if fastmem is not enabled.
 2014-09-17 20:08:09 -04:00
Fiora
02dce5dbbf x64Emitter: fix silent failure if WriteNormalOp is passed two memory operands 
Should now fail loudly and clearly instead.
 2014-09-15 07:08:08 -07:00
Fiora
997c5c2d0e x64Emitter: add LZCNT/TZCNT support and detection 
Also add a unit test.
 2014-09-14 05:31:22 -07:00
Fiora
18d83a310e X64Emitter: support shorter mov reg, imm opcodes 
Also refactor WriteNormalOp a little bit and add comments.
 2014-09-11 11:40:30 -07:00
Rohit Nirmal
fbc64984ca Include CommonTypes.h instead of Common.h. 2014-09-08 15:39:58 -04:00
Rohit Nirmal
629ceaf2b1 Split some parts of UpdateBoundingBox into multiple lines. Also, 
fix issues causing failure on Lint.
 2014-09-06 09:49:27 -05:00
Rohit Nirmal
1ecb318bcc Fix some formatting (new lines on collapsed single-line conditionals, 
new lines for opening braces).
 2014-09-06 01:23:05 -05:00
Fiora
5088a2b4e2 x64Emitter: add BMI1/BMI2 support 
TZCNT and LZCNT use a completely different encoding scheme, so they should
probably go in a separate patch.

Also add some tests.
 2014-09-03 10:04:01 -07:00
shuffle2
532b7bb7da Merge pull request #893 from rohitnirmal/scan-build-fixes 
Scan build fixes
 2014-09-02 23:15:18 -07:00
Fiora
9e4419e786 x64Emitter: add support for shorter EAX forms of instructions 
Should save a few bytes of code size here and there.
 2014-09-02 21:52:41 -07:00
Pierre Bourdon
e72146d19c x64Emitter: Do not assert-fail on redundant MOVs, instead show an error log 2014-09-02 10:17:32 +02:00
Pierre Bourdon
cc0b048c0b x64Emitter: Support FLD/FSTP with 80 bits operands 2014-09-02 09:52:59 +02:00
Pierre Bourdon
f99f302c91 x64Emitter: assert instead of crashing when generating MOVZX with a wrong size 2014-09-02 09:52:04 +02:00
Pierre Bourdon
b1738b60fc x64Emitter: Fix MUL with AH/BH/CH/DH registers. 2014-09-02 09:52:04 +02:00
Pierre Bourdon
f0e8b1fda8 x64Emitter: Error out on 8 bits CMOV, and emit 16 bits CMOV properly 2014-09-02 09:52:04 +02:00
Pierre Bourdon
d4ec9737bd x64Emitter: Assert when using an invalid POP instead of generating an INT3 2014-09-02 09:52:04 +02:00
Pierre Bourdon
9c4daac3a4 x64Emitter: RDTSC now without a typo'd name 2014-09-02 09:52:04 +02:00
Lioncash
ec9fc6bfc1 Common: Remove unnecessary "using namespace Gen;" from x64emitter 2014-09-01 23:10:56 -04:00
Lioncash
ba4934b75e Common: Clean up brace placements 2014-08-30 18:06:35 -04:00
Fiora
f9d4ff0d5d x64Emitter: add support for some missing CVT instructions 2014-08-27 20:15:42 -07:00
Rohit Nirmal
4c14ebdf32 Remove pointless initializations. 2014-08-27 20:36:49 -05:00
Tillmann Karras
80be585fef x64Emitter: remove redundant "Gen::" 2014-08-20 02:56:07 +02:00
Tillmann Karras
a363f4fa3e x64Emitter: make 'packed' parameter a bool 2014-08-20 02:54:30 +02:00
Fiora
802b28daf9 x64Emitter: refactor to support longer opcodes 
Also add some new SSE4 opcodes.
 2014-08-17 04:48:17 -07:00
Fiora
75b3e425fd x64Emitter: optimize immediate sizes 
A nice alternative than trying to do it throughout the JIT.
 2014-08-07 13:07:27 -04:00
Ryan Houdek
0c24e1dcf2 Remove the rest of x86_32 support from Common. 2014-08-03 13:49:46 -05:00
Pierre Bourdon
9b9817f927 x64Emitter: Fix REX encoding for SETcc 
Previously using the new "lower 8 bits" registers (SIL, SPL, ...) caused SETcc
to write to other registers (for example, SETcc SIL would generate SETcc DH).
 2014-07-30 06:41:29 -07:00
Tillmann Karras
6df48ed432 x64Emitter: add CVTTPD2DQ 2014-07-15 23:53:56 +02:00
Lioncash
bd377b9580 Merge pull request #443 from magumagu/loadstore-cleanup 
Loadstore cleanup
 2014-06-26 21:32:59 -04:00
Lioncash
ca5340ebde Centralize the logging code into its own folder in Common. 2014-06-25 22:11:42 -04:00
magumagu
06864e9fee JIT: Clean up float loads and stores. 
Less code is good, and this should make future changes to memory handling
easier.
 2014-06-20 12:52:39 -07:00
Tillmann Karras
f8280401f6 x64Emitter: J_CC: use 32 bit offset automatically 2014-06-03 23:08:58 +02:00
Tillmann Karras
e659f5ac58 JitBackpatch: fix NOP padding 
The new NOP emitter breaks when called with a negative count. As it
turns out, it did happen when deoptimizing 8 bit MOVs because they are
only 4 bytes long and need no BSWAP.
 2014-04-30 15:26:11 +02:00
Tillmann Karras
957649b7af Optimize NOPs 2014-04-23 21:15:09 +02:00
Pierre Bourdon
b2597739ff x64Emitter: Add the MOVBE instruction. 2014-04-11 23:33:21 +02:00
Pierre Bourdon
664c8d30a0 Remove all trailing whitespaces from our codebase. 2014-03-29 11:05:44 +01:00
magumagu
03292eabc2 Fix OpArg::WriteRex with 8-bit memory operand. 
Previously he function was misbehaving because of a missing check for
whether an 8-bit operand was a register operand; it would therefore
emit unnecessary REX prefixes, incorrectly assert on 32-bit targets, and
could potentially emit wrong code in rare cases (like a memory to register
operation involving AH.)

Also, some cleanup while I was in the area to make the function easier to
read.
 2014-03-25 14:09:15 -07:00
Matthew Parlane
31cfc73a09 Fixes spacing for "for", "while", "switch" and "if" 
Also moved && and || to ends of lines instead of start.
Fixed misc vertical alignments and some { needed newlining.
 2014-03-11 00:35:07 +13:00
Ryan Houdek
4f02132f93 Make our architecture defines less stupid. 
Our defines were never clear between what meant 64bit or x86_64
This makes a clear cut between bitness and architecture.
This commit also has the side effect of bringing up aarch64 compiling support.
 2014-03-04 09:36:59 -06:00
Pierre Bourdon
311caef094 Merge pull request #25 from Tilka/ppc_fp 
Fix non-IEEE mode
 2014-02-23 04:15:37 +01:00
Pierre Bourdon
83b7bb64aa Make Common/ mostly IWYU clean (and fix errors in rest of the project detected by this change). 2014-02-22 23:37:29 +01:00
Lioncash
2afe215271 Convert all includes to relative paths. 2014-02-18 02:19:10 -05:00
Scott Mansell
cf5938c4df x64Emitter: Fix the PSUBQ instruction's opcode 2014-02-12 23:12:17 +01:00
Scott Mansell
1eb8168488 x64Emitter: Add the xmm, xmm form of PSRLQ instruction. 2014-02-12 23:12:16 +01:00
Tillmann Karras
db196d8c5b Jit64[IL]: fix float conversions 
Floating-point is complicated...

Some background: Denormals are floats that are too close to zero to be
stored in a normalized way (their exponent would need more bits). Since
they are stored unnormalized, they are hard to work with, even in
hardware.  That's why both PowerPC and SSE can be configured to operate
in faster but non-standard-conpliant modes in which these numbers are
simply rounded ('flushed') to zero.

Internally, we do the same as the PowerPC CPU and store all floats in
double format. This means that for loading and storing singles we need a
conversion. The PowerPC CPU does this in hardware. We previously did
this using CVTSS2SD/CVTSD2SS. Unfortunately, these instructions are
considered arithmetic and therefore flush denormals to zero if non-IEEE
mode is active. This normally wouldn't be a problem since the next
arithmetic floating-point instruction would do the same anyway but as it
turns out some games actually use floating-point instructions for
copying arbitrary data.

My idea for fixing this problem was to use x87 instructions since the
x87 FPU never supported flush-to-zero and thus doesn't mangle denormals.
However, there is one more problem to deal with: SNaNs are automatically
converted to QNaNs (by setting the most-significant bit of the
fraction). I opted to fix this by manually resetting the QNaN bit of all
values with all-1s exponent.
 2014-02-12 23:12:15 +01:00
Tillmann Karras
c25c4a6e20 x64: add support for some x87 instructions 2014-02-12 22:45:01 +01:00
Tillmann Karras
b34fe2b8f1 x64: fix parameter names of WriteModRM() 2014-01-25 17:36:09 +01:00
Jasper St. Pierre
34692ab826 Remove unnecessary Src/ folders 2013-12-31 14:03:19 -05:00