Commit Graph

368 Commits

Author SHA1 Message Date
709862b818 Merge pull request #8120 from MerryMage/cdts
Jit64: Make DoubleToSingle a common asm routine
2020-01-25 19:10:37 +00:00
c6019f9814 PowerPC/Jit: Create fastmem arena on init. 2019-12-28 13:41:57 +01:00
c4799e5977 Jit64: Make DoubleToSingle a common asm routine 2019-05-25 23:07:50 +01:00
2f490e44fb stop using g_jit outside of JitInterface
Replace g_jit in x86-64 ASM routines code by m_jit member reference
2018-12-15 01:58:58 +01:00
f564da7233 Jit_LoadStoreFloating: lfXXX 2018-10-28 17:57:45 +00:00
534db3b2ed Jit_LoadStore: lXXx 2018-10-28 17:57:44 +00:00
7aa305ea35 Profiler: Migrate global g_ProfileBlocks boolean to JitOptions
This global belongs in the JitOptions structure, as it's a conditional
setting (A.K.A. option) that changes the behavior of what the JIT does.

Plus it keeps the scope of the variable constrained to the general area
it's intended to be used and nothing further.
2018-08-27 11:30:19 -04:00
e81408588f JitCommon/JitCache: Make JitBlock's checkedEntry and normalEntry members non-const pointers
In both cases of the x64 and AArch64 JITs, these would have const casted
away from them, followed by them being placed within an emitter and
having breakpoint instructions written in them.

In this case, we shouldn't be using const period if we're writing to the
emitted data.
2018-08-27 10:23:22 -04:00
a4110ad958 PowerPC: Deduplicate Helper_Mask() code
We can share this across all implementations instead of duplicating it
in different ways.
2018-08-12 17:24:16 -04:00
1f49a9c87c Merge pull request #7116 from lioncash/log
JitCommon/JitBase: Rename x86-specific logging define to be platform agnostic
2018-06-14 15:00:34 +02:00
065aba43e2 JitBase: Remove unused rewriteStart data member from JitState 2018-06-14 08:46:34 -04:00
ace24c2932 JitCommon/JitBase: Rename x86-specific logging define to be platform agnostic
Given JitBase shouldn't include platform specifics, we can generalize this
preprocessor define and allow any JIT to use it to indicate that generated code should be logged.

While we're at it, also move these defines beneath the includes with the
rest of the defines.
2018-06-14 08:35:35 -04:00
a3f2941173 JitBase: Centralize location of code buffer
Given the code buffer is something truly common to all JIT
implementations, we can centralize it in the base class and avoid
duplicating it all over the place, while still allowing for differently
sized buffers.
2018-06-09 08:16:53 -04:00
986d644a01 JitAsmCommon: Make CommonAsmRoutinesBase a struct
This is just used as a means of carting around routines. It's not meant
to directly have functionality embedded within it--this is the job of
the inheriting data structure--so we can just make this a basic struct.

Particularly given all the data members were public to begin with.
2018-05-30 05:22:41 -04:00
f5f4c10fd1 JitAsmCommon: Amend member variable names for CommonAsmRoutinesBase 2018-05-30 05:22:36 -04:00
f4ec419929 SymbolDB: Namespace code under the Common namespace
Moves more common code into the Common namespace where it belongs.
2018-05-27 18:01:40 -04:00
b9aad3310e PowerPC: Move MMU-specifics from PowerPC.h to MMU.h
PowerPC.h at this point is pretty much a general glob of stuff, and it's
unfortunate, since it means pulling in a lot of unrelated header
dependencies and a bunch of other things that don't need to be seen by
things that just want to read memory.

Breaking this out into its own header keeps all the MMU-related stuff
together and also limits the amount of header dependencies being
included (the primary motivation for this being the former reason).
2018-05-17 19:18:55 -04:00
c880302c6b Prevent paired singles routines clobbering PC,SRR0
Paired single (ps) instructions can call asm_routines that try to update
PowerPC::ppcState.pc. At the time the asm_routine is built, emulation has
not started and the PC is invalid (0). If the ps instruction causes an
exception (e.g. DSI), SRR0 gets clobbered with the invalid PC.

This change makes the relevant ps instructions store PC before calling out
to asm_routines, and prevents the asm_routine from trying to store PC
itself.
2018-05-14 20:49:13 -04:00
ffcf107dd2 PowerPC: Make the PowerPCState's msr member variable a UReg_MSR instance
Gets rid of the need to construct UReg_MSR values around the the actual
member in order to query information from it (without using shifts and
masks). This makes it more concise in some areas, while helping with
readability in some other places (such as copying the ILE bit to the LE
bit in the exception checking functions).
2018-05-05 17:59:30 -04:00
e0165a62da JitBase: Remove use of the JIT global in Dispatch() and JitTrampoline()
Trims down a few more uses of the global variable by just passing the
JIT instance we're dispatching or trampolining with as a parameter.
2018-03-21 04:41:30 -04:00
51cfeb8c7d JitBase: Ensure JitOptions and JitState instances are consistently initialized
Ensures that upon construction of a JitBase instance, that all
underlying members within the option and state structs are guaranteed
to be initialized.

This prevents potentially using a member uninitialized in some form.
2018-03-19 15:58:32 -04:00
36ad887a19 Jit64: Inline GP writes.
As we're down to 4 instructions now, it is always worth to inline those writes.
2017-11-18 14:45:09 +01:00
8cd8e9d905 JIT: Don't always look up symbols for blocks
With tons of symbols, this results in noticeable stuttering, so
skip lookups if the perf dir option isn't set anyway.
2017-09-10 11:42:12 +02:00
958b75b707 JitCommon: Restructure the profiler calls. 2017-09-02 13:05:58 +02:00
f6c21e002b General: Remove unnecessary semicolons 2017-07-30 16:39:53 -04:00
9a2bef97da JitCache: use SymbolDB names as JIT block names 2017-06-18 06:58:44 +01:00
b676edd80c Core: include what you use
Eliminates a swath of indirectly included standard headers
2017-06-07 01:20:48 -04:00
cac77527e9 Jit64: Make psq_lXX PIE-compliant 2017-04-14 11:52:33 +01:00
8d98ac6509 CPU: Convert state enum to an enum class
Gets enum constants out of the immediate namespace. Also makes it
strongly typed like the other state enums.
2017-03-28 11:48:28 -04:00
0d1bc53e55 JitBase: Rename MergeAllowedNextInstructions to CanMergeNextInstructions
This is more indicative that it's checking for something
2017-03-21 13:50:03 -04:00
f98211bfcf JitBase: Make MergeAllowedNextInstructions a const member function 2017-03-21 13:45:18 -04:00
b0d6c29073 JitAsmCommon: Add missing sizes to constant arrays
This allows generic code to determine the size of these arrays.
2017-03-20 20:21:41 +00:00
c6200a5b07 JitInterface: Convert includes into forward declarations where applicable 2017-03-02 13:20:29 -05:00
9ad6c8f334 Make memory breakpoint faster
Currently, slowmem is used at any time that memory breakpoints are in use.  This commit makes it so that whenever the DBAT gets updated, if the address is overllaping any memchecks, it forces the use of slowmem.  This allows to keep fastmem for any other cases and noticably increases performance when using memory breakpoints.
2017-03-02 04:46:27 -05:00
52fe05af6b Make memory breakpoint faster
Currently, slowmem is used at any time that memory breakpoints are in use.  This commit makes it so that whenever the DBAT gets updated, if the address is overllaping any memchecks, it forces the use of slowmem.  This allows to keep fastmem for any other cases and noticably increases performance when using memory breakpoints.
2017-02-28 13:02:04 -05:00
ffa61fcf57 JitCache: Also unlink exits of the current block.
We might still be in the current block. This is fine, but the next one might also be invalidated later on. But we may never also call the next one.
2017-02-27 23:50:16 +01:00
c1ddc2678e JitCache: Fix removing of blocks. 2017-02-27 23:50:16 +01:00
359528b805 JitBase: Put constructor and destructor in the cpp file
As this is a base class with virtuals, there needs to be an out-of-line
function definition to prevent the vtable of the class being placed within
every translation unit it's used in (i.e. every JIT implementation).
2017-02-23 13:50:47 -05:00
384efb0cb2 JitArm64: Initial implementation of the BLR optimization. 2017-02-02 09:06:34 +01:00
d3aee2de08 JitCache: Split off JIT call from dispatcher.
This avoid flushing the BLR optimization stack on fast_block_cache misses.
2017-01-25 01:51:19 +01:00
a7bf9271b5 Fix missing includes 2017-01-24 03:31:51 +01:00
7f6b8e3555 JitCache: Extract ErasePhysicalRange as function. 2017-01-23 20:33:44 +01:00
70caf447b9 JitCache: Get physical addresses from PPCAnalyst.
So we support all kind of degenerated blocks now, not just range+length based ones.
2017-01-23 20:33:44 +01:00
f3ed993747 JitCache: Use a map with macro blocks for the occupied memory regions.
This also allow fast invalidation, without any restritions on the blocks itself.
So we can now implement inlining.
2017-01-23 20:33:44 +01:00
dc0fbc15f0 JitCache: Drop block_map.
It is only used for invalidation, and in a bad way. Just scan over all elements,
as it is still in O(n), this shouldn't matter much.
2017-01-23 20:33:44 +01:00
819ebfb213 JitCache: Freeing hotfix.
Sorry, I'm too stupid to test my code.
2017-01-23 06:58:02 +01:00
8e00c411a3 JitCache::Rename iCache to fast_block_map.
iCache sounds too much like emulation.
2017-01-22 17:10:28 +01:00
830ae6a2c1 JitCache: Store the JitBlock in the std::map. 2017-01-22 16:50:46 +01:00
9b77a39767 JitCache: Only call DestroyBlock on valid blocks. 2017-01-22 16:50:46 +01:00
113d6b3b84 JitCache: Use a multimap for block_map and start_block_map.
We may have duplicated entries here because of MSR mismatch. Just
store both and validate the matching one on cache access.
2017-01-22 16:50:46 +01:00