Compare commits

...

4 Commits

Author SHA1 Message Date
Tygyh
d4e43818f7
Merge c1ff466e16 into 2c92e5b5b3 2024-11-12 15:15:54 +01:00
OatmealDome
2c92e5b5b3
Merge pull request #13160 from cpba/flatpak-6.8-runtime
Flatpak: Upgrade kde runtime to 6.8
2024-11-12 00:30:46 -05:00
Carles Pastor
fe96bf4108 Flatpak: Upgrade kde runtime to 6.8
this version bundles SDL2-2.30.6, the temporary measure of building the
vendored version from exports is no longer necessary.
2024-11-10 12:06:06 +01:00
Dr. Dystopia
c1ff466e16 Split 'IsRAMAddress' method into 'IsEffectiveRAMAddress' and 'IsPhysicalRAMAddress' methods 2024-08-20 15:31:13 +02:00
4 changed files with 18 additions and 41 deletions

View File

@ -1,22 +0,0 @@
{
"name": "SDL2",
"buildsystem": "autotools",
"config-opts": ["--disable-static"],
"sources": [
{
"type": "dir",
"path": "../../Externals/SDL/SDL"
}
],
"cleanup": [ "/bin/sdl2-config",
"/include",
"/lib/libSDL2.la",
"/lib/libSDL2main.a",
"/lib/libSDL2main.la",
"/lib/libSDL2_test.a",
"/lib/libSDL2_test.la",
"/lib/cmake",
"/share/aclocal",
"/lib/pkgconfig"]
}

View File

@ -1,6 +1,6 @@
app-id: org.DolphinEmu.dolphin-emu app-id: org.DolphinEmu.dolphin-emu
runtime: org.kde.Platform runtime: org.kde.Platform
runtime-version: '6.7' runtime-version: '6.8'
sdk: org.kde.Sdk sdk: org.kde.Sdk
command: dolphin-emu-wrapper command: dolphin-emu-wrapper
rename-desktop-file: dolphin-emu.desktop rename-desktop-file: dolphin-emu.desktop
@ -47,9 +47,6 @@ modules:
url: https://github.com/Unrud/xdg-screensaver-shim/archive/0.0.2.tar.gz url: https://github.com/Unrud/xdg-screensaver-shim/archive/0.0.2.tar.gz
sha256: 0ed2a69fe6ee6cbffd2fe16f85116db737f17fb1e79bfb812d893cf15c728399 sha256: 0ed2a69fe6ee6cbffd2fe16f85116db737f17fb1e79bfb812d893cf15c728399
# build the vendored SDL2 from Externals until the runtime gets 2.30.6
- SDL2/SDL2.json
- name: dolphin-emu - name: dolphin-emu
buildsystem: cmake-ninja buildsystem: cmake-ninja
config-opts: config-opts:

View File

@ -938,16 +938,14 @@ bool MMU::IsOptimizableRAMAddress(const u32 address, const u32 access_size) cons
} }
template <XCheckTLBFlag flag> template <XCheckTLBFlag flag>
bool MMU::IsRAMAddress(u32 address, bool translate) bool MMU::IsEffectiveRAMAddress(u32 address)
{ {
if (translate) auto translate_address = TranslateAddress<flag>(address);
{ return translate_address.Success() && IsPhysicalRAMAddress(translate_address.address);
auto translate_address = TranslateAddress<flag>(address); }
if (!translate_address.Success())
return false;
address = translate_address.address;
}
bool MMU::IsPhysicalRAMAddress(const u32 address) const
{
u32 segment = address >> 28; u32 segment = address >> 28;
if (m_memory.GetRAM() && segment == 0x0 && (address & 0x0FFFFFFF) < m_memory.GetRamSizeReal()) if (m_memory.GetRAM() && segment == 0x0 && (address & 0x0FFFFFFF) < m_memory.GetRamSizeReal())
{ {
@ -977,13 +975,14 @@ bool MMU::HostIsRAMAddress(const Core::CPUThreadGuard& guard, u32 address,
switch (space) switch (space)
{ {
case RequestedAddressSpace::Effective: case RequestedAddressSpace::Effective:
return mmu.IsRAMAddress<XCheckTLBFlag::NoException>(address, mmu.m_ppc_state.msr.DR); return mmu.m_ppc_state.msr.DR ? mmu.IsEffectiveRAMAddress<XCheckTLBFlag::NoException>(address) :
mmu.IsPhysicalRAMAddress(address);
case RequestedAddressSpace::Physical: case RequestedAddressSpace::Physical:
return mmu.IsRAMAddress<XCheckTLBFlag::NoException>(address, false); return mmu.IsPhysicalRAMAddress(address);
case RequestedAddressSpace::Virtual: case RequestedAddressSpace::Virtual:
if (!mmu.m_ppc_state.msr.DR) if (!mmu.m_ppc_state.msr.DR)
return false; return false;
return mmu.IsRAMAddress<XCheckTLBFlag::NoException>(address, true); return mmu.IsEffectiveRAMAddress<XCheckTLBFlag::NoException>(address);
} }
ASSERT(false); ASSERT(false);
@ -1001,13 +1000,15 @@ bool MMU::HostIsInstructionRAMAddress(const Core::CPUThreadGuard& guard, u32 add
switch (space) switch (space)
{ {
case RequestedAddressSpace::Effective: case RequestedAddressSpace::Effective:
return mmu.IsRAMAddress<XCheckTLBFlag::OpcodeNoException>(address, mmu.m_ppc_state.msr.IR); return mmu.m_ppc_state.msr.IR ?
mmu.IsEffectiveRAMAddress<XCheckTLBFlag::OpcodeNoException>(address) :
mmu.IsPhysicalRAMAddress(address);
case RequestedAddressSpace::Physical: case RequestedAddressSpace::Physical:
return mmu.IsRAMAddress<XCheckTLBFlag::OpcodeNoException>(address, false); return mmu.IsPhysicalRAMAddress(address);
case RequestedAddressSpace::Virtual: case RequestedAddressSpace::Virtual:
if (!mmu.m_ppc_state.msr.IR) if (!mmu.m_ppc_state.msr.IR)
return false; return false;
return mmu.IsRAMAddress<XCheckTLBFlag::OpcodeNoException>(address, true); return mmu.IsEffectiveRAMAddress<XCheckTLBFlag::OpcodeNoException>(address);
} }
ASSERT(false); ASSERT(false);

View File

@ -310,7 +310,8 @@ private:
template <XCheckTLBFlag flag, bool never_translate = false> template <XCheckTLBFlag flag, bool never_translate = false>
void WriteToHardware(u32 em_address, const u32 data, const u32 size); void WriteToHardware(u32 em_address, const u32 data, const u32 size);
template <XCheckTLBFlag flag> template <XCheckTLBFlag flag>
bool IsRAMAddress(u32 address, bool translate); bool IsEffectiveRAMAddress(u32 address);
bool IsPhysicalRAMAddress(u32 address) const;
template <typename T> template <typename T>
static std::optional<ReadResult<T>> HostTryReadUX(const Core::CPUThreadGuard& guard, static std::optional<ReadResult<T>> HostTryReadUX(const Core::CPUThreadGuard& guard,