Files
dolphin/Source/Core/Core
Sintendo 1c25e6352a Jit64: addx - Emit nothing when possible
When the destination register matches a source register, the other
source register contains zero, and overflow isn't needed, the
instruction becomes a nop and we don't need to emit anything.

We could add specialized handling for the case where overflow is needed,
but none of the titles I tried would hit this path.

Before:
83 C7 00             add         edi,0

After:
2020-04-21 22:35:17 +02:00
..
2020-03-30 17:46:50 +04:00
2020-01-31 20:45:08 +00:00
2020-01-04 11:43:33 -08:00
2019-07-18 22:29:04 +02:00