mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2024-11-14 21:37:52 -07:00
937bb2aa2e
Fixes LIT (https://bugs.dolphin-emu.org/issues/13635). The text does not include normals, but has lighting enabled. With the previous default of (0, 0, 0), lighting was always black (as dot(X, (0, 0, 0)) is always 0). It seems like the normal from the map in the background (0, 0, 1) is re-used. LIT also has the vertex color enabled while vertex color is not specified, the same as SMS's debug cubes; the default MissingColorValue GameINI value of solid white seems to work correctly in this case.
535 lines
20 KiB
C++
535 lines
20 KiB
C++
// Copyright 2015 Dolphin Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "VideoCommon/VertexLoaderARM64.h"
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#include <array>
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#include "Common/CommonTypes.h"
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#include "VideoCommon/CPMemory.h"
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#include "VideoCommon/VertexLoaderManager.h"
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using namespace Arm64Gen;
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constexpr ARM64Reg src_reg = ARM64Reg::X0;
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constexpr ARM64Reg dst_reg = ARM64Reg::X1;
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constexpr ARM64Reg remaining_reg = ARM64Reg::W2;
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constexpr ARM64Reg skipped_reg = ARM64Reg::W17;
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constexpr ARM64Reg scratch1_reg = ARM64Reg::W16;
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constexpr ARM64Reg scratch2_reg = ARM64Reg::W15;
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constexpr ARM64Reg scratch3_reg = ARM64Reg::W14;
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constexpr ARM64Reg saved_count = ARM64Reg::W12;
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constexpr ARM64Reg stride_reg = ARM64Reg::X11;
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constexpr ARM64Reg arraybase_reg = ARM64Reg::X10;
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constexpr ARM64Reg scale_reg = ARM64Reg::X9;
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static constexpr int GetLoadSize(int load_bytes)
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{
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if (load_bytes == 1)
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return 1;
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else if (load_bytes <= 2)
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return 2;
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else if (load_bytes <= 4)
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return 4;
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else if (load_bytes <= 8)
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return 8;
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else
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return 16;
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}
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alignas(16) static const float scale_factors[] = {
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1.0 / (1ULL << 0), 1.0 / (1ULL << 1), 1.0 / (1ULL << 2), 1.0 / (1ULL << 3),
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1.0 / (1ULL << 4), 1.0 / (1ULL << 5), 1.0 / (1ULL << 6), 1.0 / (1ULL << 7),
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1.0 / (1ULL << 8), 1.0 / (1ULL << 9), 1.0 / (1ULL << 10), 1.0 / (1ULL << 11),
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1.0 / (1ULL << 12), 1.0 / (1ULL << 13), 1.0 / (1ULL << 14), 1.0 / (1ULL << 15),
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1.0 / (1ULL << 16), 1.0 / (1ULL << 17), 1.0 / (1ULL << 18), 1.0 / (1ULL << 19),
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1.0 / (1ULL << 20), 1.0 / (1ULL << 21), 1.0 / (1ULL << 22), 1.0 / (1ULL << 23),
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1.0 / (1ULL << 24), 1.0 / (1ULL << 25), 1.0 / (1ULL << 26), 1.0 / (1ULL << 27),
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1.0 / (1ULL << 28), 1.0 / (1ULL << 29), 1.0 / (1ULL << 30), 1.0 / (1ULL << 31),
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};
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VertexLoaderARM64::VertexLoaderARM64(const TVtxDesc& vtx_desc, const VAT& vtx_att)
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: VertexLoaderBase(vtx_desc, vtx_att), m_float_emit(this)
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{
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AllocCodeSpace(4096);
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const Common::ScopedJITPageWriteAndNoExecute enable_jit_page_writes;
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ClearCodeSpace();
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GenerateVertexLoader();
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WriteProtect(true);
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}
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// Returns the register to use as the base and an offset from that register.
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// For indexed attributes, the index is read into scratch1_reg, and then scratch1_reg with no offset
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// is returned. For direct attributes, an offset from src_reg is returned.
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std::pair<Arm64Gen::ARM64Reg, u32> VertexLoaderARM64::GetVertexAddr(CPArray array,
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VertexComponentFormat attribute)
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{
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if (IsIndexed(attribute))
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{
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if (attribute == VertexComponentFormat::Index8)
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{
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LDURB(scratch1_reg, src_reg, m_src_ofs);
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m_src_ofs += 1;
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}
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else // Index16
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{
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LDURH(scratch1_reg, src_reg, m_src_ofs);
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m_src_ofs += 2;
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REV16(scratch1_reg, scratch1_reg);
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}
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if (array == CPArray::Position)
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{
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EOR(scratch2_reg, scratch1_reg,
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attribute == VertexComponentFormat::Index8 ? LogicalImm(0xFF, GPRSize::B32) :
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LogicalImm(0xFFFF, GPRSize::B32));
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m_skip_vertex = CBZ(scratch2_reg);
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}
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LDR(IndexType::Unsigned, scratch2_reg, stride_reg, static_cast<u8>(array) * 4);
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MUL(scratch1_reg, scratch1_reg, scratch2_reg);
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LDR(IndexType::Unsigned, EncodeRegTo64(scratch2_reg), arraybase_reg,
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static_cast<u8>(array) * 8);
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ADD(EncodeRegTo64(scratch1_reg), EncodeRegTo64(scratch1_reg), EncodeRegTo64(scratch2_reg));
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return {EncodeRegTo64(scratch1_reg), 0};
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}
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else
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{
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return {src_reg, m_src_ofs};
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}
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}
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void VertexLoaderARM64::ReadVertex(VertexComponentFormat attribute, ComponentFormat format,
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int count_in, int count_out, bool dequantize,
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u8 scaling_exponent, AttributeFormat* native_format,
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ARM64Reg reg, u32 offset)
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{
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ARM64Reg coords = count_in == 3 ? ARM64Reg::Q31 : ARM64Reg::D31;
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ARM64Reg scale = count_in == 3 ? ARM64Reg::Q30 : ARM64Reg::D30;
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int elem_size = GetElementSize(format);
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int load_bytes = elem_size * count_in;
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int load_size = GetLoadSize(load_bytes);
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load_size <<= 3;
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m_float_emit.LDUR(load_size, coords, reg, offset);
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if (format < ComponentFormat::Float)
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{
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// Extend and convert to float
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switch (format)
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{
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case ComponentFormat::UByte:
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m_float_emit.UXTL(8, EncodeRegToDouble(coords), EncodeRegToDouble(coords));
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m_float_emit.UXTL(16, EncodeRegToDouble(coords), EncodeRegToDouble(coords));
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break;
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case ComponentFormat::Byte:
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m_float_emit.SXTL(8, EncodeRegToDouble(coords), EncodeRegToDouble(coords));
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m_float_emit.SXTL(16, EncodeRegToDouble(coords), EncodeRegToDouble(coords));
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break;
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case ComponentFormat::UShort:
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m_float_emit.REV16(8, EncodeRegToDouble(coords), EncodeRegToDouble(coords));
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m_float_emit.UXTL(16, EncodeRegToDouble(coords), EncodeRegToDouble(coords));
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break;
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case ComponentFormat::Short:
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m_float_emit.REV16(8, EncodeRegToDouble(coords), EncodeRegToDouble(coords));
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m_float_emit.SXTL(16, EncodeRegToDouble(coords), EncodeRegToDouble(coords));
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break;
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}
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m_float_emit.SCVTF(32, coords, coords);
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if (dequantize && scaling_exponent)
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{
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m_float_emit.LDR(32, IndexType::Unsigned, scale, scale_reg, scaling_exponent * 4);
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m_float_emit.FMUL(32, coords, coords, scale, 0);
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}
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}
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else
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{
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m_float_emit.REV32(8, coords, coords);
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}
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const u32 write_size = count_out == 3 ? 128 : count_out * 32;
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m_float_emit.STUR(write_size, coords, dst_reg, m_dst_ofs);
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// Z-Freeze
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if (native_format == &m_native_vtx_decl.position)
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{
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CMP(remaining_reg, 3);
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FixupBranch dont_store = B(CC_GE);
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MOVP2R(EncodeRegTo64(scratch2_reg), VertexLoaderManager::position_cache.data());
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m_float_emit.STR(128, coords, EncodeRegTo64(scratch2_reg), ArithOption(remaining_reg, true));
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SetJumpTarget(dont_store);
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}
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else if (native_format == &m_native_vtx_decl.normals[0])
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{
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FixupBranch dont_store = CBNZ(remaining_reg);
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MOVP2R(EncodeRegTo64(scratch2_reg), VertexLoaderManager::normal_cache.data());
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m_float_emit.STR(128, IndexType::Unsigned, coords, EncodeRegTo64(scratch2_reg), 0);
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SetJumpTarget(dont_store);
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}
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else if (native_format == &m_native_vtx_decl.normals[1])
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{
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FixupBranch dont_store = CBNZ(remaining_reg);
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MOVP2R(EncodeRegTo64(scratch2_reg), VertexLoaderManager::tangent_cache.data());
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m_float_emit.STR(128, IndexType::Unsigned, coords, EncodeRegTo64(scratch2_reg), 0);
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SetJumpTarget(dont_store);
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}
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else if (native_format == &m_native_vtx_decl.normals[2])
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{
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FixupBranch dont_store = CBNZ(remaining_reg);
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MOVP2R(EncodeRegTo64(scratch2_reg), VertexLoaderManager::binormal_cache.data());
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m_float_emit.STR(128, IndexType::Unsigned, coords, EncodeRegTo64(scratch2_reg), 0);
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SetJumpTarget(dont_store);
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}
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native_format->components = count_out;
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native_format->enable = true;
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native_format->offset = m_dst_ofs;
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native_format->type = ComponentFormat::Float;
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native_format->integer = false;
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m_dst_ofs += sizeof(float) * count_out;
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if (attribute == VertexComponentFormat::Direct)
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m_src_ofs += load_bytes;
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}
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void VertexLoaderARM64::ReadColor(VertexComponentFormat attribute, ColorFormat format, ARM64Reg reg,
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u32 offset)
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{
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int load_bytes = 0;
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switch (format)
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{
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case ColorFormat::RGB888:
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case ColorFormat::RGB888x:
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case ColorFormat::RGBA8888:
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LDUR(scratch2_reg, reg, offset);
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if (format != ColorFormat::RGBA8888)
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ORR(scratch2_reg, scratch2_reg, LogicalImm(0xFF000000, GPRSize::B32));
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STR(IndexType::Unsigned, scratch2_reg, dst_reg, m_dst_ofs);
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load_bytes = format == ColorFormat::RGB888 ? 3 : 4;
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break;
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case ColorFormat::RGB565:
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// RRRRRGGG GGGBBBBB
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// AAAAAAAA BBBBBBBB GGGGGGGG RRRRRRRR
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LDURH(scratch3_reg, reg, offset);
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REV16(scratch3_reg, scratch3_reg);
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// B
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AND(scratch2_reg, scratch3_reg, LogicalImm(0x1F, GPRSize::B32));
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ORR(scratch2_reg, ARM64Reg::WSP, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSL, 3));
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ORR(scratch2_reg, scratch2_reg, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSR, 5));
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ORR(scratch1_reg, ARM64Reg::WSP, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSL, 16));
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// G
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UBFM(scratch2_reg, scratch3_reg, 5, 10);
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ORR(scratch2_reg, ARM64Reg::WSP, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSL, 2));
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ORR(scratch2_reg, scratch2_reg, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSR, 6));
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSL, 8));
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// R
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UBFM(scratch2_reg, scratch3_reg, 11, 15);
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSL, 3));
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSR, 2));
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// A
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ORR(scratch1_reg, scratch1_reg, LogicalImm(0xFF000000, GPRSize::B32));
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STR(IndexType::Unsigned, scratch1_reg, dst_reg, m_dst_ofs);
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load_bytes = 2;
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break;
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case ColorFormat::RGBA4444:
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// BBBBAAAA RRRRGGGG
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// REV16 - RRRRGGGG BBBBAAAA
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// AAAAAAAA BBBBBBBB GGGGGGGG RRRRRRRR
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LDURH(scratch3_reg, reg, offset);
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// R
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UBFM(scratch1_reg, scratch3_reg, 4, 7);
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// G
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AND(scratch2_reg, scratch3_reg, LogicalImm(0xF, GPRSize::B32));
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSL, 8));
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// B
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UBFM(scratch2_reg, scratch3_reg, 12, 15);
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSL, 16));
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// A
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UBFM(scratch2_reg, scratch3_reg, 8, 11);
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSL, 24));
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// Final duplication
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ORR(scratch1_reg, scratch1_reg, scratch1_reg, ArithOption(scratch1_reg, ShiftType::LSL, 4));
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STR(IndexType::Unsigned, scratch1_reg, dst_reg, m_dst_ofs);
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load_bytes = 2;
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break;
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case ColorFormat::RGBA6666:
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// RRRRRRGG GGGGBBBB BBAAAAAA
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// AAAAAAAA BBBBBBBB GGGGGGGG RRRRRRRR
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LDUR(scratch3_reg, reg, offset - 1);
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REV32(scratch3_reg, scratch3_reg);
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// A
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UBFM(scratch2_reg, scratch3_reg, 0, 5);
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ORR(scratch2_reg, ARM64Reg::WSP, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSL, 2));
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ORR(scratch2_reg, scratch2_reg, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSR, 6));
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ORR(scratch1_reg, ARM64Reg::WSP, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSL, 24));
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// B
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UBFM(scratch2_reg, scratch3_reg, 6, 11);
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ORR(scratch2_reg, ARM64Reg::WSP, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSL, 2));
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ORR(scratch2_reg, scratch2_reg, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSR, 6));
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSL, 16));
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// G
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UBFM(scratch2_reg, scratch3_reg, 12, 17);
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ORR(scratch2_reg, ARM64Reg::WSP, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSL, 2));
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ORR(scratch2_reg, scratch2_reg, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSR, 6));
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSL, 8));
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// R
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UBFM(scratch2_reg, scratch3_reg, 18, 23);
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSL, 2));
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ShiftType::LSR, 4));
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STR(IndexType::Unsigned, scratch1_reg, dst_reg, m_dst_ofs);
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load_bytes = 3;
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break;
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}
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if (attribute == VertexComponentFormat::Direct)
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m_src_ofs += load_bytes;
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}
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void VertexLoaderARM64::GenerateVertexLoader()
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{
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// The largest input vertex (with the position matrix index and all texture matrix indices
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// enabled, and all components set as direct) is 129 bytes (corresponding to a 156-byte
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// output). This is small enough that we can always use the unscaled load/store instructions
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// (which allow an offset from -256 to +255).
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ASSERT(m_vertex_size <= 255);
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// R0 - Source pointer
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// R1 - Destination pointer
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// R2 - Count
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// R30 - LR
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//
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// R0 return how many
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//
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// Registers we don't have to worry about saving
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// R9-R17 are caller saved temporaries
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// R18 is a temporary or platform specific register(iOS)
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//
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// VFP registers
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// We can touch all except v8-v15
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// If we need to use those, we need to retain the lower 64bits(!) of the register
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bool has_tc = false;
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bool has_tc_scale = false;
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for (size_t i = 0; i < m_VtxDesc.high.TexCoord.Size(); i++)
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{
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has_tc |= m_VtxDesc.high.TexCoord[i] != VertexComponentFormat::NotPresent;
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has_tc_scale |= (m_VtxAttr.GetTexFrac(i) != 0);
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}
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bool need_scale = (m_VtxAttr.g0.ByteDequant && m_VtxAttr.g0.PosFrac) ||
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(has_tc && has_tc_scale) ||
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(m_VtxDesc.low.Normal != VertexComponentFormat::NotPresent);
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AlignCode16();
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if (IsIndexed(m_VtxDesc.low.Position))
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MOV(skipped_reg, ARM64Reg::WZR);
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ADD(saved_count, remaining_reg, 1);
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MOVP2R(stride_reg, g_main_cp_state.array_strides.data());
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MOVP2R(arraybase_reg, VertexLoaderManager::cached_arraybases.data());
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if (need_scale)
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MOVP2R(scale_reg, scale_factors);
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const u8* loop_start = GetCodePtr();
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if (m_VtxDesc.low.PosMatIdx)
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{
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LDRB(IndexType::Unsigned, scratch1_reg, src_reg, m_src_ofs);
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AND(scratch1_reg, scratch1_reg, LogicalImm(0x3F, GPRSize::B32));
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STR(IndexType::Unsigned, scratch1_reg, dst_reg, m_dst_ofs);
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// Z-Freeze
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CMP(remaining_reg, 3);
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FixupBranch dont_store = B(CC_GE);
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MOVP2R(EncodeRegTo64(scratch2_reg), VertexLoaderManager::position_matrix_index_cache.data());
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STR(scratch1_reg, EncodeRegTo64(scratch2_reg), ArithOption(remaining_reg, true));
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SetJumpTarget(dont_store);
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m_native_vtx_decl.posmtx.components = 4;
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m_native_vtx_decl.posmtx.enable = true;
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m_native_vtx_decl.posmtx.offset = m_dst_ofs;
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m_native_vtx_decl.posmtx.type = ComponentFormat::UByte;
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m_native_vtx_decl.posmtx.integer = true;
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m_src_ofs += sizeof(u8);
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m_dst_ofs += sizeof(u32);
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}
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std::array<u32, 8> texmatidx_ofs;
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for (size_t i = 0; i < m_VtxDesc.low.TexMatIdx.Size(); i++)
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{
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if (m_VtxDesc.low.TexMatIdx[i])
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texmatidx_ofs[i] = m_src_ofs++;
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}
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// Position
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{
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const int pos_elements = m_VtxAttr.g0.PosElements == CoordComponentCount::XY ? 2 : 3;
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const auto [reg, offset] = GetVertexAddr(CPArray::Position, m_VtxDesc.low.Position);
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ReadVertex(m_VtxDesc.low.Position, m_VtxAttr.g0.PosFormat, pos_elements, pos_elements,
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m_VtxAttr.g0.ByteDequant, m_VtxAttr.g0.PosFrac, &m_native_vtx_decl.position, reg,
|
|
offset);
|
|
}
|
|
|
|
if (m_VtxDesc.low.Normal != VertexComponentFormat::NotPresent)
|
|
{
|
|
static constexpr Common::EnumMap<u8, ComponentFormat::InvalidFloat7> SCALE_MAP = {7, 6, 15, 14,
|
|
0, 0, 0, 0};
|
|
const u8 scaling_exponent = SCALE_MAP[m_VtxAttr.g0.NormalFormat];
|
|
|
|
// Normal
|
|
auto [reg, offset] = GetVertexAddr(CPArray::Normal, m_VtxDesc.low.Normal);
|
|
ReadVertex(m_VtxDesc.low.Normal, m_VtxAttr.g0.NormalFormat, 3, 3, true, scaling_exponent,
|
|
&m_native_vtx_decl.normals[0], reg, offset);
|
|
|
|
if (m_VtxAttr.g0.NormalElements == NormalComponentCount::NTB)
|
|
{
|
|
const bool index3 = IsIndexed(m_VtxDesc.low.Normal) && m_VtxAttr.g0.NormalIndex3;
|
|
const int elem_size = GetElementSize(m_VtxAttr.g0.NormalFormat);
|
|
const int load_bytes = elem_size * 3;
|
|
|
|
// Tangent
|
|
// If in Index3 mode, and indexed components are used, replace the index with a new index.
|
|
if (index3)
|
|
std::tie(reg, offset) = GetVertexAddr(CPArray::Normal, m_VtxDesc.low.Normal);
|
|
// The tangent comes after the normal; even in index3 mode, an extra offset of load_bytes is
|
|
// applied. Note that this is different from adding 1 to the index, as the stride for indices
|
|
// may be different from the size of the tangent itself.
|
|
ReadVertex(m_VtxDesc.low.Normal, m_VtxAttr.g0.NormalFormat, 3, 3, true, scaling_exponent,
|
|
&m_native_vtx_decl.normals[1], reg, offset + load_bytes);
|
|
// Binormal
|
|
if (index3)
|
|
std::tie(reg, offset) = GetVertexAddr(CPArray::Normal, m_VtxDesc.low.Normal);
|
|
ReadVertex(m_VtxDesc.low.Normal, m_VtxAttr.g0.NormalFormat, 3, 3, true, scaling_exponent,
|
|
&m_native_vtx_decl.normals[2], reg, offset + load_bytes * 2);
|
|
}
|
|
}
|
|
|
|
for (u8 i = 0; i < m_VtxDesc.low.Color.Size(); i++)
|
|
{
|
|
m_native_vtx_decl.colors[i].components = 4;
|
|
m_native_vtx_decl.colors[i].type = ComponentFormat::UByte;
|
|
m_native_vtx_decl.colors[i].integer = false;
|
|
|
|
if (m_VtxDesc.low.Color[i] != VertexComponentFormat::NotPresent)
|
|
{
|
|
const auto [reg, offset] = GetVertexAddr(CPArray::Color0 + i, m_VtxDesc.low.Color[i]);
|
|
ReadColor(m_VtxDesc.low.Color[i], m_VtxAttr.GetColorFormat(i), reg, offset);
|
|
m_native_vtx_decl.colors[i].components = 4;
|
|
m_native_vtx_decl.colors[i].enable = true;
|
|
m_native_vtx_decl.colors[i].offset = m_dst_ofs;
|
|
m_native_vtx_decl.colors[i].type = ComponentFormat::UByte;
|
|
m_native_vtx_decl.colors[i].integer = false;
|
|
m_dst_ofs += 4;
|
|
}
|
|
}
|
|
|
|
for (u8 i = 0; i < m_VtxDesc.high.TexCoord.Size(); i++)
|
|
{
|
|
m_native_vtx_decl.texcoords[i].offset = m_dst_ofs;
|
|
m_native_vtx_decl.texcoords[i].type = ComponentFormat::Float;
|
|
m_native_vtx_decl.texcoords[i].integer = false;
|
|
|
|
const int elements = m_VtxAttr.GetTexElements(i) == TexComponentCount::S ? 1 : 2;
|
|
if (m_VtxDesc.high.TexCoord[i] != VertexComponentFormat::NotPresent)
|
|
{
|
|
const auto [reg, offset] = GetVertexAddr(CPArray::TexCoord0 + i, m_VtxDesc.high.TexCoord[i]);
|
|
u8 scaling_exponent = m_VtxAttr.GetTexFrac(i);
|
|
ReadVertex(m_VtxDesc.high.TexCoord[i], m_VtxAttr.GetTexFormat(i), elements,
|
|
m_VtxDesc.low.TexMatIdx[i] ? 2 : elements, m_VtxAttr.g0.ByteDequant,
|
|
scaling_exponent, &m_native_vtx_decl.texcoords[i], reg, offset);
|
|
}
|
|
if (m_VtxDesc.low.TexMatIdx[i])
|
|
{
|
|
m_native_vtx_decl.texcoords[i].components = 3;
|
|
m_native_vtx_decl.texcoords[i].enable = true;
|
|
m_native_vtx_decl.texcoords[i].type = ComponentFormat::Float;
|
|
m_native_vtx_decl.texcoords[i].integer = false;
|
|
|
|
LDRB(IndexType::Unsigned, scratch2_reg, src_reg, texmatidx_ofs[i]);
|
|
m_float_emit.UCVTF(ARM64Reg::S31, scratch2_reg);
|
|
|
|
if (m_VtxDesc.high.TexCoord[i] != VertexComponentFormat::NotPresent)
|
|
{
|
|
m_float_emit.STR(32, IndexType::Unsigned, ARM64Reg::D31, dst_reg, m_dst_ofs);
|
|
m_dst_ofs += sizeof(float);
|
|
}
|
|
else
|
|
{
|
|
m_native_vtx_decl.texcoords[i].offset = m_dst_ofs;
|
|
|
|
STUR(ARM64Reg::SP, dst_reg, m_dst_ofs);
|
|
m_float_emit.STR(32, IndexType::Unsigned, ARM64Reg::D31, dst_reg, m_dst_ofs + 8);
|
|
|
|
m_dst_ofs += sizeof(float) * 3;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Prepare for the next vertex.
|
|
ADD(dst_reg, dst_reg, m_dst_ofs);
|
|
const u8* cont = GetCodePtr();
|
|
ADD(src_reg, src_reg, m_src_ofs);
|
|
|
|
SUBS(remaining_reg, remaining_reg, 1);
|
|
B(CCFlags::CC_GE, loop_start);
|
|
|
|
if (IsIndexed(m_VtxDesc.low.Position))
|
|
{
|
|
SUB(ARM64Reg::W0, saved_count, skipped_reg);
|
|
RET(ARM64Reg::X30);
|
|
|
|
SetJumpTarget(m_skip_vertex);
|
|
ADD(skipped_reg, skipped_reg, 1);
|
|
B(cont);
|
|
}
|
|
else
|
|
{
|
|
MOV(ARM64Reg::W0, saved_count);
|
|
RET(ARM64Reg::X30);
|
|
}
|
|
|
|
FlushIcache();
|
|
|
|
ASSERT_MSG(VIDEO, m_vertex_size == m_src_ofs,
|
|
"Vertex size from vertex loader ({}) does not match expected vertex size ({})!\nVtx "
|
|
"desc: {:08x} {:08x}\nVtx attr: {:08x} {:08x} {:08x}",
|
|
m_src_ofs, m_vertex_size, m_VtxDesc.low.Hex, m_VtxDesc.high.Hex, m_VtxAttr.g0.Hex,
|
|
m_VtxAttr.g1.Hex, m_VtxAttr.g2.Hex);
|
|
m_native_vtx_decl.stride = m_dst_ofs;
|
|
}
|
|
|
|
int VertexLoaderARM64::RunVertices(const u8* src, u8* dst, int count)
|
|
{
|
|
m_numLoadedVertices += count;
|
|
return ((int (*)(const u8* src, u8* dst, int count))region)(src, dst, count - 1);
|
|
}
|