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895b02f410
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3563 8ced0084-cf51-0410-be5f-012b33b47a6e
463 lines
10 KiB
C++
463 lines
10 KiB
C++
/*====================================================================
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filename: opcodes.h
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project: GameCube DSP Tool (gcdsp)
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created: 2005.03.04
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mail: duddie@walla.com
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Copyright (c) 2005 Duddie
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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====================================================================*/
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#include "DSPIntUtil.h"
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#include "DSPMemoryMap.h"
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// Extended opcodes do not exist on their own. These opcodes can only be
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// attached to opcodes that allow extending (8 lower bits of opcode not used by
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// opcode). Extended opcodes do not modify program counter $pc register.
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// Most of the suffixes increment or decrement one or more addressing registers
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// (the first four, ARx). The increment/decrement is either 1, or the corresponding
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// "index" register (the second four, IXx). The addressing registers will wrap
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// in odd ways, dictated by the corresponding wrapping register, WP0-3.
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// The following should be applied as a decrement (and is applied by dsp_decrement_addr_reg):
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// ar[i] = (ar[i] & wp[i]) == 0 ? ar[i] | wp[i] : ar[i] - 1;
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// I have not found the corresponding algorithms for increments yet.
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// It's gotta be fairly simple though. See R3123, R3125 in Google Code.
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// (May have something to do with (ar[i] ^ wp[i]) == 0)
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/*
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namespace DSPInterpreter
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{
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namespace Ext
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{
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// DR $arR
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// xxxx xxxx 0000 01rr
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// Decrement addressing register $arR.
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void dr(const UDSPInstruction& opc) {
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dsp_decrement_addr_reg(opc.hex & 0x3);
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}
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// IR $arR
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// xxxx xxxx 0000 10rr
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// Increment addressing register $arR.
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void ir(const UDSPInstruction& opc) {
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dsp_increment_addr_reg(opc.hex & 0x3);
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}
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// NR $arR
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// xxxx xxxx 0000 11rr
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// Add corresponding indexing register $ixR to addressing register $arR.
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void nr(const UDSPInstruction& opc) {
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u8 reg = opc.hex & 0x3;
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// g_dsp.r[reg] += g_dsp.r[reg + DSP_REG_IX0];
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dsp_increase_addr_reg(reg, (s16)g_dsp.r[DSP_REG_IX0 + reg]);
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}
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// MV $axD, $acS.l
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// xxxx xxxx 0001 ddss
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// Move value of $acS.l to the $axD.l.
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void mv(const UDSPInstruction& opc)
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{
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u8 sreg = opc.hex & 0x3;
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u8 dreg = ((opc.hex >> 2) & 0x3);
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g_dsp.r[dreg + DSP_REG_AXL0] = g_dsp.r[sreg + DSP_REG_ACC0];
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}
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// S @$D, $acD.l
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// xxxx xxxx 001s s0dd
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// Store value of $(acS.l) in the memory pointed by register $D.
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// Post increment register $D.
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void s(const UDSPInstruction& opc)
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{
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u8 dreg = opc.hex & 0x3;
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u8 sreg = ((opc.hex >> 3) & 0x3) + DSP_REG_ACC0;
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dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
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dsp_increment_addr_reg(dreg);
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}
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// SN @$D, $acD.l
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// xxxx xxxx 001s s1dd
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// Store value of register $acS in the memory pointed by register $D.
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// Add indexing register $ixD to register $D.
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void sn(const UDSPInstruction& opc)
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{
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u8 dreg = opc.hex & 0x3;
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u8 sreg = ((opc.hex >> 3) & 0x3) + DSP_REG_ACC0;
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dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
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// g_dsp.r[dreg] += g_dsp.r[dreg + DSP_REG_IX0];
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dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]);
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}
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// L axD.l, @$S
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// xxxx xxxx 01dd d0ss
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// Load $axD with value from memory pointed by register $S.
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// Post increment register $S.
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void l(const UDSPInstruction& opc)
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{
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u8 sreg = opc.hex & 0x3;
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u8 dreg = ((opc.hex >> 3) & 0x7) + DSP_REG_AXL0;
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u16 val = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[dreg] = val;
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dsp_increment_addr_reg(sreg);
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}
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// LN axD.l, @$S
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// xxxx xxxx 01dd d0ss
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// Load $axD with value from memory pointed by register $S.
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// Add indexing register register $ixS to register $S.
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void ln(const UDSPInstruction& opc)
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{
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u8 sreg = opc.hex & 0x3;
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u8 dreg = ((opc.hex >> 3) & 0x7) + DSP_REG_AXL0;
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u16 val = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[dreg] = val;
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// g_dsp.r[sreg] += g_dsp.r[sreg + DSP_REG_IX0];
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dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
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}
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// Not in duddie's doc
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// LD $ax0.d $ax1.r @$arS
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// xxxx xxxx 11dr 00ss
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void ld(const UDSPInstruction& opc)
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{
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u8 dreg = (((opc.hex >> 5) & 0x1) << 1) + DSP_REG_AXL0;
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u8 rreg = (((opc.hex >> 4) & 0x1) << 1) + DSP_REG_AXL1;
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u8 sreg = opc.hex & 0x3;
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g_dsp.r[dreg] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[rreg] = dsp_dmem_read(g_dsp.r[DSP_REG_AR3]);
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dsp_increment_addr_reg(sreg);
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dsp_increment_addr_reg(DSP_REG_AR3);
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}
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// Not in duddie's doc
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// LDN $ax0.d $ax1.r @$arS
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// xxxx xxxx 11dr 01ss
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void ldn(const UDSPInstruction& opc)
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{
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u8 dreg = (((opc.hex >> 5) & 0x1) << 1) + DSP_REG_AXL0;
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u8 rreg = (((opc.hex >> 4) & 0x1) << 1) + DSP_REG_AXL1;
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u8 sreg = opc.hex & 0x3;
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g_dsp.r[dreg] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[rreg] = dsp_dmem_read(g_dsp.r[DSP_REG_AR3]);
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g_dsp.r[sreg] += g_dsp.r[sreg + DSP_REG_IX0];
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dsp_increment_addr_reg(DSP_REG_AR3);
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}
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// Not in duddie's doc
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// LDM $ax0.d $ax1.r @$arS
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// xxxx xxxx 11dr 10ss
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void ldm(const UDSPInstruction& opc)
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{
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u8 dreg = (((opc.hex >> 5) & 0x1) << 1) + DSP_REG_AXL0;
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u8 rreg = (((opc.hex >> 4) & 0x1) << 1) + DSP_REG_AXL1;
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u8 sreg = opc.hex & 0x3;
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g_dsp.r[dreg] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[rreg] = dsp_dmem_read(g_dsp.r[DSP_REG_AR3]);
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dsp_increment_addr_reg(sreg);
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g_dsp.r[DSP_REG_AR3] += g_dsp.r[DSP_REG_IX3];
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}
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// Not in duddie's doc
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// LDNM $ax0.d $ax1.r @$arS
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// xxxx xxxx 11dr 11ss
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void ldnm(const UDSPInstruction& opc)
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{
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u8 dreg = (((opc.hex >> 5) & 0x1) << 1) + DSP_REG_AXL0;
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u8 rreg = (((opc.hex >> 4) & 0x1) << 1) + DSP_REG_AXL1;
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u8 sreg = opc.hex & 0x3;
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g_dsp.r[dreg] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[rreg] = dsp_dmem_read(g_dsp.r[DSP_REG_AR3]);
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g_dsp.r[sreg] += g_dsp.r[sreg + DSP_REG_IX0];
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g_dsp.r[DSP_REG_AR3] += g_dsp.r[DSP_REG_IX3];
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}
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} // end namespace ext
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} // end namespace DSPInterpeter
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*/
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void dsp_op_ext_r_epi(const UDSPInstruction& opc)
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{
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u8 op = (opc.hex >> 2) & 0x3;
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u8 reg = opc.hex & 0x3;
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switch (op) {
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case 0x00: //
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g_dsp.r[reg] = 0;
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break;
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case 0x01: // DR
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dsp_decrement_addr_reg(reg);
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break;
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case 0x02: // IR
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dsp_increment_addr_reg(reg);
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break;
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case 0x03: // NR
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// g_dsp.r[reg] += g_dsp.r[reg + 4];
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dsp_increase_addr_reg(reg, (s16)g_dsp.r[DSP_REG_IX0 + reg]);
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break;
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}
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}
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void dsp_op_ext_mv(const UDSPInstruction& opc)
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{
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u8 sreg = opc.hex & 0x3;
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u8 dreg = ((opc.hex >> 2) & 0x3);
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g_dsp.r[dreg + 0x18] = g_dsp.r[sreg + 0x1c];
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}
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void dsp_op_ext_s(const UDSPInstruction& opc)
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{
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u8 dreg = opc.hex & 0x3;
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u8 sreg = ((opc.hex >> 3) & 0x3) + 0x1c;
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dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
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if (opc.hex & 0x04) // SN
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{
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// g_dsp.r[dreg] += g_dsp.r[dreg + 4];
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dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]);
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}
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else
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{
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dsp_increment_addr_reg(dreg); // S
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}
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}
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void dsp_op_ext_l(const UDSPInstruction& opc)
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{
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u8 sreg = opc.hex & 0x3;
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u8 dreg = ((opc.hex >> 3) & 0x7) + DSP_REG_AXL0;
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u16 val = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[dreg] = val;
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if (opc.hex & 0x04) // LN/LSMN
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{
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dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
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// g_dsp.r[sreg] += g_dsp.r[sreg + 4];
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}
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else
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{
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dsp_increment_addr_reg(sreg); // LS
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}
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}
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void dsp_op_ext_ls_pro(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex & 0x1) + 0x1e;
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dsp_dmem_write(g_dsp.r[0x03], g_dsp.r[areg]);
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u8 sreg = 0x03;
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if (opc.hex & 0x8) // LSM/LSMN
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{
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dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
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// g_dsp.r[0x03] += g_dsp.r[0x07];
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}
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else // LS
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{
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dsp_increment_addr_reg(sreg);
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}
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}
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void dsp_op_ext_ls_epi(const UDSPInstruction& opc)
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{
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u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
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u16 val = dsp_dmem_read(g_dsp.r[0x00]);
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dsp_op_write_reg(dreg, val);
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if (opc.hex & 0x4) // LSN/LSMN
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{
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//g_dsp.r[0x00] += g_dsp.r[0x04];
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dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]);
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}
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else // LS
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{
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dsp_increment_addr_reg(0x00);
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}
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}
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void dsp_op_ext_sl_pro(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex & 0x1) + 0x1e;
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dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
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if (opc.hex & 0x4) // SLN/SLNM
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{
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dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]);
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// g_dsp.r[0x00] += g_dsp.r[0x04];
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}
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else // SL
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{
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dsp_increment_addr_reg(0x00);
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}
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}
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void dsp_op_ext_sl_epi(const UDSPInstruction& opc)
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{
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u8 dreg = ((opc.hex >> 4) & 0x3) + 0x18;
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u16 val = dsp_dmem_read(g_dsp.r[0x03]);
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dsp_op_write_reg(dreg, val);
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u8 sreg = 0x03;
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if (opc.hex & 0x8) // SLM/SLMN
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{
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dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
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// g_dsp.r[0x03] += g_dsp.r[0x07];
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}
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else // SL
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{
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dsp_increment_addr_reg(sreg);
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}
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}
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void dsp_op_ext_ld(const UDSPInstruction& opc)
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{
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u8 dreg1 = (((opc.hex >> 5) & 0x1) << 1) + 0x18;
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u8 dreg2 = (((opc.hex >> 4) & 0x1) << 1) + 0x19;
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u8 sreg = opc.hex & 0x3;
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g_dsp.r[dreg1] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[dreg2] = dsp_dmem_read(g_dsp.r[0x03]);
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if (opc.hex & 0x04) // N
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{
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dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
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//g_dsp.r[sreg] += g_dsp.r[sreg + 0x04];
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}
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else
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{
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dsp_increment_addr_reg(sreg);
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}
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if (opc.hex & 0x08) // M
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{
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dsp_increase_addr_reg(0x03, (s16)g_dsp.r[DSP_REG_IX0 + 0x03]);
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// g_dsp.r[0x03] += g_dsp.r[0x07];
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}
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else
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{
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dsp_increment_addr_reg(0x03);
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}
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}
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// ================================================================================
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//
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//
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//
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// ================================================================================
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void dsp_op_ext_ops_pro(const UDSPInstruction& opc)
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{
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if ((opc.hex & 0xFF) == 0){return;}
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switch ((opc.hex >> 4) & 0xf)
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{
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case 0x00:
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dsp_op_ext_r_epi(opc.hex);
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break;
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case 0x01:
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dsp_op_ext_mv(opc.hex);
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break;
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case 0x02:
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case 0x03:
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dsp_op_ext_s(opc.hex);
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break;
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case 0x04:
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case 0x05:
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case 0x06:
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case 0x07:
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dsp_op_ext_l(opc.hex);
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break;
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case 0x08:
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case 0x09:
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case 0x0a:
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case 0x0b:
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if (opc.hex & 0x2)
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dsp_op_ext_sl_pro(opc.hex);
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else
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dsp_op_ext_ls_pro(opc.hex);
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break;
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case 0x0c:
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case 0x0d:
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case 0x0e:
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case 0x0f:
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dsp_op_ext_ld(opc.hex);
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break;
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}
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}
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void dsp_op_ext_ops_epi(const UDSPInstruction& opc)
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{
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if ((opc.hex & 0xFF) == 0)
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return;
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switch ((opc.hex >> 4) & 0xf)
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{
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case 0x08:
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case 0x09:
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case 0x0a:
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case 0x0b:
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if (opc.hex & 0x2)
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{
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dsp_op_ext_sl_epi(opc.hex);
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}
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else
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{
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dsp_op_ext_ls_epi(opc.hex);
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}
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break;
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|
return;
|
|
}
|
|
}
|