mirror of
https://github.com/dolphin-emu/dolphin.git
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715d5ae8a7
This implements a partial JITIL based off of the JIT64IL. It's enough to run most games, albiet at a slow speed. Implementing instructions for this IL is really simple since it basically is just enabling based on what is already in JIT64IL, and then enabling each individual IL instruction.
769 lines
22 KiB
C++
769 lines
22 KiB
C++
// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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// WARNING - THIS LIBRARY IS NOT THREAD SAFE!!!
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#ifndef _DOLPHIN_ARM_CODEGEN_
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#define _DOLPHIN_ARM_CODEGEN_
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#include "Common.h"
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#include "MemoryUtil.h"
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#if defined(__SYMBIAN32__) || defined(PANDORA)
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#include <signal.h>
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#endif
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#include <vector>
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#undef _IP
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#undef R0
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#undef _SP
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#undef _LR
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#undef _PC
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// VCVT flags
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#define TO_FLOAT 0
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#define TO_INT 1 << 0
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#define IS_SIGNED 1 << 1
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#define ROUND_TO_ZERO 1 << 2
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namespace ArmGen
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{
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enum ARMReg
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{
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// GPRs
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R0 = 0, R1, R2, R3, R4, R5,
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R6, R7, R8, R9, R10, R11,
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// SPRs
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// R13 - R15 are SP, LR, and PC.
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// Almost always referred to by name instead of register number
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R12 = 12, R13 = 13, R14 = 14, R15 = 15,
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_IP = 12, _SP = 13, _LR = 14, _PC = 15,
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// VFP single precision registers
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S0, S1, S2, S3, S4, S5, S6,
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S7, S8, S9, S10, S11, S12, S13,
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S14, S15, S16, S17, S18, S19, S20,
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S21, S22, S23, S24, S25, S26, S27,
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S28, S29, S30, S31,
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// VFP Double Precision registers
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D0, D1, D2, D3, D4, D5, D6, D7,
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D8, D9, D10, D11, D12, D13, D14, D15,
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D16, D17, D18, D19, D20, D21, D22, D23,
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D24, D25, D26, D27, D28, D29, D30, D31,
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// ASIMD Quad-Word registers
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Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
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Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15,
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INVALID_REG = 0xFFFFFFFF
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};
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enum CCFlags
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{
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CC_EQ = 0, // Equal
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CC_NEQ, // Not equal
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CC_CS, // Carry Set
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CC_CC, // Carry Clear
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CC_MI, // Minus (Negative)
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CC_PL, // Plus
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CC_VS, // Overflow
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CC_VC, // No Overflow
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CC_HI, // Unsigned higher
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CC_LS, // Unsigned lower or same
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CC_GE, // Signed greater than or equal
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CC_LT, // Signed less than
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CC_GT, // Signed greater than
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CC_LE, // Signed less than or equal
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CC_AL, // Always (unconditional) 14
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CC_HS = CC_CS, // Alias of CC_CS Unsigned higher or same
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CC_LO = CC_CC, // Alias of CC_CC Unsigned lower
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};
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const u32 NO_COND = 0xE0000000;
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enum ShiftType
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{
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ST_LSL = 0,
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ST_ASL = 0,
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ST_LSR = 1,
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ST_ASR = 2,
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ST_ROR = 3,
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ST_RRX = 4
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};
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enum
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{
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NUMGPRs = 13,
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};
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class ARMXEmitter;
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enum OpType
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{
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TYPE_IMM = 0,
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TYPE_REG,
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TYPE_IMMSREG,
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TYPE_RSR,
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TYPE_MEM
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};
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// This is no longer a proper operand2 class. Need to split up.
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class Operand2
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{
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friend class ARMXEmitter;
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protected:
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u32 Value;
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private:
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OpType Type;
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// IMM types
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u8 Rotation; // Only for u8 values
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// Register types
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u8 IndexOrShift;
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ShiftType Shift;
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public:
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OpType GetType()
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{
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return Type;
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}
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Operand2() {}
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Operand2(u32 imm, OpType type = TYPE_IMM)
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{
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Type = type;
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Value = imm;
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Rotation = 0;
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}
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Operand2(ARMReg Reg)
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{
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Type = TYPE_REG;
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Value = Reg;
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Rotation = 0;
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}
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Operand2(u8 imm, u8 rotation)
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{
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Type = TYPE_IMM;
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Value = imm;
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Rotation = rotation;
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}
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Operand2(ARMReg base, ShiftType type, ARMReg shift) // RSR
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{
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Type = TYPE_RSR;
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_assert_msg_(DYNA_REC, type != ST_RRX, "Invalid Operand2: RRX does not take a register shift amount");
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IndexOrShift = shift;
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Shift = type;
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Value = base;
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}
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Operand2(ARMReg base, ShiftType type, u8 shift)// For IMM shifted register
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{
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if(shift == 32) shift = 0;
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switch (type)
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{
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case ST_LSL:
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_assert_msg_(DYNA_REC, shift < 32, "Invalid Operand2: LSL %u", shift);
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break;
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case ST_LSR:
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_assert_msg_(DYNA_REC, shift <= 32, "Invalid Operand2: LSR %u", shift);
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if (!shift)
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type = ST_LSL;
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if (shift == 32)
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shift = 0;
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break;
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case ST_ASR:
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_assert_msg_(DYNA_REC, shift < 32, "Invalid Operand2: LSR %u", shift);
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if (!shift)
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type = ST_LSL;
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if (shift == 32)
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shift = 0;
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break;
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case ST_ROR:
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_assert_msg_(DYNA_REC, shift < 32, "Invalid Operand2: ROR %u", shift);
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if (!shift)
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type = ST_LSL;
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break;
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case ST_RRX:
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_assert_msg_(DYNA_REC, shift == 0, "Invalid Operand2: RRX does not take an immediate shift amount");
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type = ST_ROR;
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break;
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}
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IndexOrShift = shift;
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Shift = type;
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Value = base;
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Type = TYPE_IMMSREG;
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}
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u32 GetData()
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{
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switch(Type)
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{
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case TYPE_IMM:
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return Imm12Mod(); // This'll need to be changed later
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case TYPE_REG:
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return Rm();
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case TYPE_IMMSREG:
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return IMMSR();
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case TYPE_RSR:
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return RSR();
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default:
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_assert_msg_(DYNA_REC, false, "GetData with Invalid Type");
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return 0;
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}
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}
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u32 IMMSR() // IMM shifted register
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{
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_assert_msg_(DYNA_REC, Type == TYPE_IMMSREG, "IMMSR must be imm shifted register");
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return ((IndexOrShift & 0x1f) << 7 | (Shift << 5) | Value);
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}
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u32 RSR() // Register shifted register
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{
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_assert_msg_(DYNA_REC, Type == TYPE_RSR, "RSR must be RSR Of Course");
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return (IndexOrShift << 8) | (Shift << 5) | 0x10 | Value;
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}
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u32 Rm()
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{
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_assert_msg_(DYNA_REC, Type == TYPE_REG, "Rm must be with Reg");
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return Value;
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}
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u32 Imm5()
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{
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_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm5 not IMM value");
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return ((Value & 0x0000001F) << 7);
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}
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u32 Imm8()
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{
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_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm8Rot not IMM value");
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return Value & 0xFF;
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}
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u32 Imm8Rot() // IMM8 with Rotation
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{
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_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm8Rot not IMM value");
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_assert_msg_(DYNA_REC, (Rotation & 0xE1) != 0, "Invalid Operand2: immediate rotation %u", Rotation);
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return (1 << 25) | (Rotation << 7) | (Value & 0x000000FF);
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}
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u32 Imm12()
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{
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_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm12 not IMM");
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return (Value & 0x00000FFF);
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}
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u32 Imm12Mod()
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{
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// This is a IMM12 with the top four bits being rotation and the
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// bottom eight being a IMM. This is for instructions that need to
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// expand a 8bit IMM to a 32bit value and gives you some rotation as
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// well.
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// Each rotation rotates to the right by 2 bits
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_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm12Mod not IMM");
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return ((Rotation & 0xF) << 8) | (Value & 0xFF);
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}
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u32 Imm16()
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{
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_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm16 not IMM");
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return ( (Value & 0xF000) << 4) | (Value & 0x0FFF);
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}
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u32 Imm16Low()
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{
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return Imm16();
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}
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u32 Imm16High() // Returns high 16bits
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{
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_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm16 not IMM");
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return ( ((Value >> 16) & 0xF000) << 4) | ((Value >> 16) & 0x0FFF);
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}
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u32 Imm24()
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{
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_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm16 not IMM");
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return (Value & 0x0FFFFFFF);
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}
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// NEON and ASIMD specific
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u32 Imm8ASIMD()
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{
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_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm8ASIMD not IMM");
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return ((Value & 0x80) << 17) | ((Value & 0x70) << 12) | (Value & 0xF);
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}
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u32 Imm8VFP()
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{
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_assert_msg_(DYNA_REC, (Type == TYPE_IMM), "Imm8VFP not IMM");
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return ((Value & 0xF0) << 12) | (Value & 0xF);
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}
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};
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// Use these when you don't know if an imm can be represented as an operand2.
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// This lets you generate both an optimal and a fallback solution by checking
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// the return value, which will be false if these fail to find a Operand2 that
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// represents your 32-bit imm value.
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bool TryMakeOperand2(u32 imm, Operand2 &op2);
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bool TryMakeOperand2_AllowInverse(u32 imm, Operand2 &op2, bool *inverse);
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bool TryMakeOperand2_AllowNegation(s32 imm, Operand2 &op2, bool *negated);
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// Use this only when you know imm can be made into an Operand2.
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Operand2 AssumeMakeOperand2(u32 imm);
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inline Operand2 R(ARMReg Reg) { return Operand2(Reg, TYPE_REG); }
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inline Operand2 IMM(u32 Imm) { return Operand2(Imm, TYPE_IMM); }
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inline Operand2 Mem(void *ptr) { return Operand2((u32)ptr, TYPE_IMM); }
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//usage: struct {int e;} s; STRUCT_OFFSET(s,e)
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#define STRUCT_OFF(str,elem) ((u32)((u32)&(str).elem-(u32)&(str)))
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struct FixupBranch
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{
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u8 *ptr;
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u32 condition; // Remembers our codition at the time
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int type; //0 = B 1 = BL
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};
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struct LiteralPool
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{
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s32 loc;
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u8* ldr_address;
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u32 val;
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};
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typedef const u8* JumpTarget;
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u32 EncodeVd(ARMReg Vd);
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u32 EncodeVn(ARMReg Vn);
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u32 EncodeVm(ARMReg Vm);
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// Subtracts the base from the register to give us the real one
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ARMReg SubBase(ARMReg Reg);
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class ARMXEmitter
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{
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friend struct OpArg; // for Write8 etc
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friend class NEONXEmitter;
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private:
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u8 *code, *startcode;
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u8 *lastCacheFlushEnd;
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u32 condition;
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std::vector<LiteralPool> currentLitPool;
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void WriteStoreOp(u32 Op, ARMReg Rt, ARMReg Rn, Operand2 op2, bool RegAdd);
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void WriteRegStoreOp(u32 op, ARMReg dest, bool WriteBack, u16 RegList);
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void WriteShiftedDataOp(u32 op, bool SetFlags, ARMReg dest, ARMReg src, Operand2 op2);
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void WriteSignedMultiply(u32 Op, u32 Op2, u32 Op3, ARMReg dest, ARMReg r1, ARMReg r2);
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void WriteVFPDataOp(u32 Op, ARMReg Vd, ARMReg Vn, ARMReg Vm);
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void WriteVFPDataOp6bit(u32 Op, ARMReg Vd, ARMReg Vn, ARMReg Vm, u32 bit6);
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void Write4OpMultiply(u32 op, ARMReg destLo, ARMReg destHi, ARMReg rn, ARMReg rm);
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// New Ops
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void WriteInstruction(u32 op, ARMReg Rd, ARMReg Rn, Operand2 Rm, bool SetFlags = false);
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protected:
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inline void Write32(u32 value) {*(u32*)code = value; code+=4;}
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public:
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ARMXEmitter() : code(0), startcode(0), lastCacheFlushEnd(0) {
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condition = CC_AL << 28;
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}
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ARMXEmitter(u8 *code_ptr) {
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code = code_ptr;
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lastCacheFlushEnd = code_ptr;
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startcode = code_ptr;
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condition = CC_AL << 28;
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}
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virtual ~ARMXEmitter() {}
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void SetCodePtr(u8 *ptr);
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void ReserveCodeSpace(u32 bytes);
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const u8 *AlignCode16();
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const u8 *AlignCodePage();
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const u8 *GetCodePtr() const;
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void FlushIcache();
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void FlushIcacheSection(u8 *start, u8 *end);
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u8 *GetWritableCodePtr();
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void FlushLitPool();
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void AddNewLit(u32 val);
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bool TrySetValue_TwoOp(ARMReg reg, u32 val);
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CCFlags GetCC() { return CCFlags(condition >> 28); }
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void SetCC(CCFlags cond = CC_AL);
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// Special purpose instructions
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// Dynamic Endian Switching
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void SETEND(bool BE);
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// Debug Breakpoint
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void BKPT(u16 arg);
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// Hint instruction
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void YIELD();
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// Do nothing
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void NOP(int count = 1); //nop padding - TODO: fast nop slides, for amd and intel (check their manuals)
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#ifdef CALL
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#undef CALL
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#endif
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// Branching
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FixupBranch B();
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FixupBranch B_CC(CCFlags Cond);
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void B_CC(CCFlags Cond, const void *fnptr);
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FixupBranch BL();
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FixupBranch BL_CC(CCFlags Cond);
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void SetJumpTarget(FixupBranch const &branch);
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void B (const void *fnptr);
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void B (ARMReg src);
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void BL(const void *fnptr);
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void BL(ARMReg src);
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bool BLInRange(const void *fnptr);
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void PUSH(const int num, ...);
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void POP(const int num, ...);
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// New Data Ops
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void AND (ARMReg Rd, ARMReg Rn, Operand2 Rm);
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void ANDS(ARMReg Rd, ARMReg Rn, Operand2 Rm);
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void EOR (ARMReg dest, ARMReg src, Operand2 op2);
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void EORS(ARMReg dest, ARMReg src, Operand2 op2);
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void SUB (ARMReg dest, ARMReg src, Operand2 op2);
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void SUBS(ARMReg dest, ARMReg src, Operand2 op2);
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void RSB (ARMReg dest, ARMReg src, Operand2 op2);
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void RSBS(ARMReg dest, ARMReg src, Operand2 op2);
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void ADD (ARMReg dest, ARMReg src, Operand2 op2);
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void ADDS(ARMReg dest, ARMReg src, Operand2 op2);
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void ADC (ARMReg dest, ARMReg src, Operand2 op2);
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void ADCS(ARMReg dest, ARMReg src, Operand2 op2);
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void LSL (ARMReg dest, ARMReg src, Operand2 op2);
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void LSLS(ARMReg dest, ARMReg src, Operand2 op2);
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void LSR (ARMReg dest, ARMReg src, Operand2 op2);
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void LSRS(ARMReg dest, ARMReg src, Operand2 op2);
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void ASR (ARMReg dest, ARMReg src, Operand2 op2);
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void ASRS(ARMReg dest, ARMReg src, Operand2 op2);
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void SBC (ARMReg dest, ARMReg src, Operand2 op2);
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void SBCS(ARMReg dest, ARMReg src, Operand2 op2);
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void RBIT(ARMReg dest, ARMReg src);
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void REV (ARMReg dest, ARMReg src);
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void REV16 (ARMReg dest, ARMReg src);
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void RSC (ARMReg dest, ARMReg src, Operand2 op2);
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void RSCS(ARMReg dest, ARMReg src, Operand2 op2);
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void TST ( ARMReg src, Operand2 op2);
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void TEQ ( ARMReg src, Operand2 op2);
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void CMP ( ARMReg src, Operand2 op2);
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void CMN ( ARMReg src, Operand2 op2);
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void ORR (ARMReg dest, ARMReg src, Operand2 op2);
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void ORRS(ARMReg dest, ARMReg src, Operand2 op2);
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void MOV (ARMReg dest, Operand2 op2);
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void MOVS(ARMReg dest, Operand2 op2);
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void BIC (ARMReg dest, ARMReg src, Operand2 op2); // BIC = ANDN
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void BICS(ARMReg dest, ARMReg src, Operand2 op2);
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void MVN (ARMReg dest, Operand2 op2);
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void MVNS(ARMReg dest, Operand2 op2);
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void MOVW(ARMReg dest, Operand2 op2);
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void MOVT(ARMReg dest, Operand2 op2, bool TopBits = false);
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// UDIV and SDIV are only available on CPUs that have
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// the idiva hardare capacity
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void UDIV(ARMReg dest, ARMReg dividend, ARMReg divisor);
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void SDIV(ARMReg dest, ARMReg dividend, ARMReg divisor);
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void MUL (ARMReg dest, ARMReg src, ARMReg op2);
|
|
void MULS(ARMReg dest, ARMReg src, ARMReg op2);
|
|
|
|
void UMULL(ARMReg destLo, ARMReg destHi, ARMReg rn, ARMReg rm);
|
|
void UMULLS(ARMReg destLo, ARMReg destHi, ARMReg rn, ARMReg rm);
|
|
void SMULL(ARMReg destLo, ARMReg destHi, ARMReg rn, ARMReg rm);
|
|
|
|
void UMLAL(ARMReg destLo, ARMReg destHi, ARMReg rn, ARMReg rm);
|
|
void SMLAL(ARMReg destLo, ARMReg destHi, ARMReg rn, ARMReg rm);
|
|
|
|
void SXTB(ARMReg dest, ARMReg op2);
|
|
void SXTH(ARMReg dest, ARMReg op2, u8 rotation = 0);
|
|
void SXTAH(ARMReg dest, ARMReg src, ARMReg op2, u8 rotation = 0);
|
|
void BFI(ARMReg rd, ARMReg rn, u8 lsb, u8 width);
|
|
void UBFX(ARMReg dest, ARMReg op2, u8 lsb, u8 width);
|
|
void CLZ(ARMReg rd, ARMReg rm);
|
|
|
|
// Using just MSR here messes with our defines on the PPC side of stuff (when this code was in dolphin...)
|
|
// Just need to put an underscore here, bit annoying.
|
|
void _MSR (bool nzcvq, bool g, Operand2 op2);
|
|
void _MSR (bool nzcvq, bool g, ARMReg src);
|
|
void MRS (ARMReg dest);
|
|
|
|
// Memory load/store operations
|
|
void LDR (ARMReg dest, ARMReg base, Operand2 op2 = 0, bool RegAdd = true);
|
|
void LDRB (ARMReg dest, ARMReg base, Operand2 op2 = 0, bool RegAdd = true);
|
|
void LDRH (ARMReg dest, ARMReg base, Operand2 op2 = 0, bool RegAdd = true);
|
|
void LDRSB(ARMReg dest, ARMReg base, Operand2 op2 = 0, bool RegAdd = true);
|
|
void LDRSH(ARMReg dest, ARMReg base, Operand2 op2 = 0, bool RegAdd = true);
|
|
void STR (ARMReg result, ARMReg base, Operand2 op2 = 0, bool RegAdd = true);
|
|
void STRB (ARMReg result, ARMReg base, Operand2 op2 = 0, bool RegAdd = true);
|
|
void STRH (ARMReg result, ARMReg base, Operand2 op2 = 0, bool RegAdd = true);
|
|
|
|
void STMFD(ARMReg dest, bool WriteBack, const int Regnum, ...);
|
|
void LDMFD(ARMReg dest, bool WriteBack, const int Regnum, ...);
|
|
|
|
// Exclusive Access operations
|
|
void LDREX(ARMReg dest, ARMReg base);
|
|
// result contains the result if the instruction managed to store the value
|
|
void STREX(ARMReg result, ARMReg base, ARMReg op);
|
|
void DMB ();
|
|
void SVC(Operand2 op);
|
|
|
|
// NEON and ASIMD instructions
|
|
// None of these will be created with conditional since ARM
|
|
// is deprecating conditional execution of ASIMD instructions.
|
|
// ASIMD instructions don't even have a conditional encoding.
|
|
|
|
// VFP Only
|
|
void VLDR(ARMReg Dest, ARMReg Base, s16 offset);
|
|
void VSTR(ARMReg Src, ARMReg Base, s16 offset);
|
|
void VCMP(ARMReg Vd, ARMReg Vm);
|
|
void VCMPE(ARMReg Vd, ARMReg Vm);
|
|
// Compares against zero
|
|
void VCMP(ARMReg Vd);
|
|
void VCMPE(ARMReg Vd);
|
|
|
|
void VNMLA(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VNMLS(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VNMUL(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VDIV(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VSQRT(ARMReg Vd, ARMReg Vm);
|
|
|
|
// NEON and VFP
|
|
void VADD(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VSUB(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VABS(ARMReg Vd, ARMReg Vm);
|
|
void VNEG(ARMReg Vd, ARMReg Vm);
|
|
void VMUL(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VMLA(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VMLS(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VMOV(ARMReg Dest, Operand2 op2);
|
|
void VMOV(ARMReg Dest, ARMReg Src, bool high);
|
|
void VMOV(ARMReg Dest, ARMReg Src);
|
|
void VCVT(ARMReg Dest, ARMReg Src, int flags);
|
|
|
|
void VMRS(ARMReg Rt);
|
|
void VMSR(ARMReg Rt);
|
|
|
|
void QuickCallFunction(ARMReg scratchreg, void *func);
|
|
|
|
// Wrapper around MOVT/MOVW with fallbacks.
|
|
void MOVI2R(ARMReg reg, u32 val, bool optimize = true);
|
|
void MOVI2F(ARMReg dest, float val, ARMReg tempReg, bool negate = false);
|
|
|
|
void ADDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch);
|
|
void ANDI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch);
|
|
void CMPI2R(ARMReg rs, u32 val, ARMReg scratch);
|
|
void ORI2R(ARMReg rd, ARMReg rs, u32 val, ARMReg scratch);
|
|
|
|
|
|
}; // class ARMXEmitter
|
|
|
|
enum NEONElementType
|
|
{
|
|
I_8 = (1 << 0),
|
|
I_16 = (1 << 1),
|
|
I_32 = (1 << 2),
|
|
I_64 = (1 << 3),
|
|
I_SIGNED = (1 << 4),
|
|
I_UNSIGNED = (1 << 5),
|
|
F_32 = (1 << 6)
|
|
};
|
|
|
|
enum NEONAlignment
|
|
{
|
|
ALIGN_NONE = 0,
|
|
ALIGN_64 = 1,
|
|
ALIGN_128 = 2,
|
|
ALIGN_256 = 3
|
|
};
|
|
|
|
|
|
class NEONXEmitter
|
|
{
|
|
private:
|
|
ARMXEmitter *_emit;
|
|
inline void Write32(u32 value) { _emit->Write32(value); }
|
|
|
|
inline u32 encodedSize(u32 value)
|
|
{
|
|
if (value & I_8)
|
|
return 0;
|
|
else if (value & I_16)
|
|
return 1;
|
|
else if ((value & I_32) || (value & F_32))
|
|
return 2;
|
|
else if (value & I_64)
|
|
return 3;
|
|
else
|
|
_dbg_assert_msg_(DYNA_REC, false, "Passed invalid size to integer NEON instruction");
|
|
return 0;
|
|
}
|
|
|
|
void VREVX(u32 size, NEONElementType Size, ARMReg Vd, ARMReg Vm);
|
|
|
|
public:
|
|
NEONXEmitter(ARMXEmitter *emit)
|
|
: _emit(emit)
|
|
{}
|
|
|
|
void VABA(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VABAL(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VABD(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VABDL(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VABS(NEONElementType Size, ARMReg Vd, ARMReg Vm);
|
|
void VACGE(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VACGT(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VACLE(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VACLT(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VADD(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VADDHN(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VADDL(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VADDW(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VAND(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VBIC(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VBIF(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VBIT(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VBSL(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VCEQ(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VCEQ(NEONElementType Size, ARMReg Vd, ARMReg Vm);
|
|
void VCGE(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VCGE(NEONElementType Size, ARMReg Vd, ARMReg Vm);
|
|
void VCGT(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VCGT(NEONElementType Size, ARMReg Vd, ARMReg Vm);
|
|
void VCLE(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VCLE(NEONElementType Size, ARMReg Vd, ARMReg Vm);
|
|
void VCLS(NEONElementType Size, ARMReg Vd, ARMReg Vm);
|
|
void VCLT(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VCLT(NEONElementType Size, ARMReg Vd, ARMReg Vm);
|
|
void VCLZ(NEONElementType Size, ARMReg Vd, ARMReg Vm);
|
|
void VCNT(NEONElementType Size, ARMReg Vd, ARMReg Vm);
|
|
void VDUP(NEONElementType Size, ARMReg Vd, ARMReg Vm, u8 index);
|
|
void VDUP(NEONElementType Size, ARMReg Vd, ARMReg Rt);
|
|
void VEOR(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VEXT(ARMReg Vd, ARMReg Vn, ARMReg Vm, u8 index);
|
|
void VFMA(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VFMS(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VHADD(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VHSUB(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VMAX(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VMIN(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VMLA(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VMLS(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VMLAL(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VMLSL(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VSUB(NEONElementType Size, ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
void VREV64(NEONElementType Size, ARMReg Vd, ARMReg Vm);
|
|
void VREV32(NEONElementType Size, ARMReg Vd, ARMReg Vm);
|
|
void VREV16(NEONElementType Size, ARMReg Vd, ARMReg Vm);
|
|
|
|
void VRSQRTE(NEONElementType Size, ARMReg Vd, ARMReg Vm);
|
|
|
|
void VORR(ARMReg Vd, ARMReg Vn, ARMReg Vm);
|
|
|
|
void VLD1(NEONElementType Size, ARMReg Vd, ARMReg Rn, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
|
|
void VLD2(NEONElementType Size, ARMReg Vd, ARMReg Rn, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
|
|
|
|
void VST1(NEONElementType Size, ARMReg Vd, ARMReg Rn, NEONAlignment align = ALIGN_NONE, ARMReg Rm = _PC);
|
|
};
|
|
|
|
// Everything that needs to generate X86 code should inherit from this.
|
|
// You get memory management for free, plus, you can use all the MOV etc functions without
|
|
// having to prefix them with gen-> or something similar.
|
|
class ARMXCodeBlock : public ARMXEmitter
|
|
{
|
|
protected:
|
|
u8 *region;
|
|
size_t region_size;
|
|
|
|
public:
|
|
ARMXCodeBlock() : region(NULL), region_size(0) {}
|
|
virtual ~ARMXCodeBlock() { if (region) FreeCodeSpace(); }
|
|
|
|
// Call this before you generate any code.
|
|
void AllocCodeSpace(int size)
|
|
{
|
|
region_size = size;
|
|
region = (u8*)AllocateExecutableMemory(region_size);
|
|
SetCodePtr(region);
|
|
}
|
|
|
|
// Always clear code space with breakpoints, so that if someone accidentally executes
|
|
// uninitialized, it just breaks into the debugger.
|
|
void ClearCodeSpace()
|
|
{
|
|
// x86/64: 0xCC = breakpoint
|
|
memset(region, 0xCC, region_size);
|
|
ResetCodePtr();
|
|
}
|
|
|
|
// Call this when shutting down. Don't rely on the destructor, even though it'll do the job.
|
|
void FreeCodeSpace()
|
|
{
|
|
#ifndef __SYMBIAN32__
|
|
FreeMemoryPages(region, region_size);
|
|
#endif
|
|
region = NULL;
|
|
region_size = 0;
|
|
}
|
|
|
|
bool IsInSpace(u8 *ptr)
|
|
{
|
|
return ptr >= region && ptr < region + region_size;
|
|
}
|
|
|
|
// Cannot currently be undone. Will write protect the entire code region.
|
|
// Start over if you need to change the code (call FreeCodeSpace(), AllocCodeSpace()).
|
|
void WriteProtect()
|
|
{
|
|
WriteProtectMemory(region, region_size, true);
|
|
}
|
|
void UnWriteProtect()
|
|
{
|
|
UnWriteProtectMemory(region, region_size, false);
|
|
}
|
|
|
|
void ResetCodePtr()
|
|
{
|
|
SetCodePtr(region);
|
|
}
|
|
|
|
size_t GetSpaceLeft() const
|
|
{
|
|
return region_size - (GetCodePtr() - region);
|
|
}
|
|
|
|
u8 *GetBasePtr() {
|
|
return region;
|
|
}
|
|
|
|
size_t GetOffset(u8 *ptr) {
|
|
return ptr - region;
|
|
}
|
|
};
|
|
|
|
// VFP Specific
|
|
struct VFPEnc {
|
|
s16 opc1;
|
|
s16 opc2;
|
|
};
|
|
extern const VFPEnc VFPOps[16][2];
|
|
extern const char *VFPOpNames[16];
|
|
|
|
} // namespace
|
|
|
|
#endif // _DOLPHIN_INTEL_CODEGEN_
|