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558 lines
15 KiB
C++
558 lines
15 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: dis_decode.cc 11873 2013-10-10 21:00:26Z sshwarts $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2005-2012 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include "disasm.h"
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#include "dis_tables.h"
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#define OPCODE(entry) ((BxDisasmOpcodeInfo_t*) entry->OpcodeInfo)
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#define OPCODE_TABLE(entry) ((BxDisasmOpcodeTable_t*) entry->OpcodeInfo)
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static const unsigned char instruction_has_modrm[512] = {
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/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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/* ------------------------------- */
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/* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
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/* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
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/* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
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/* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
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/* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0,
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/* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
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/* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* A0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* B0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* C0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0,
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/* D0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1,
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/* E0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* F0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1,
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/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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/* ------------------------------- */
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1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0F 00 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 10 */
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1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,1, /* 0F 20 */
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0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 0F 30 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 40 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 50 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 60 */
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1,1,1,1,1,1,1,0,1,1,0,0,1,1,1,1, /* 0F 70 */
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0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0F 80 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 90 */
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0,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1, /* 0F A0 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F B0 */
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1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 0F C0 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F D0 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F E0 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* 0F F0 */
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/* ------------------------------- */
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/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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};
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unsigned disassembler::disasm(bx_bool is_32, bx_bool is_64, bx_address cs_base, bx_address ip, const Bit8u *instr, char *disbuf)
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{
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x86_insn insn = decode(is_32, is_64, cs_base, ip, instr, disbuf);
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return insn.ilen;
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}
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x86_insn disassembler::decode(bx_bool is_32, bx_bool is_64, bx_address cs_base, bx_address ip, const Bit8u *instr, char *disbuf)
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{
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if (is_64) is_32 = 1;
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x86_insn insn(is_32, is_64);
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const Bit8u *instruction_begin = instruction = instr;
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resolve_modrm = NULL;
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db_eip = ip;
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db_cs_base = cs_base; // cs linear base (cs_base for PM & cs<<4 for RM & VM)
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disbufptr = disbuf; // start sprintf()'ing into beginning of buffer
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#define SSE_PREFIX_NONE 0
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#define SSE_PREFIX_66 1
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#define SSE_PREFIX_F3 2
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#define SSE_PREFIX_F2 3 /* only one SSE prefix could be used */
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unsigned sse_prefix = SSE_PREFIX_NONE, sse_opcode = 0;
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unsigned rex_prefix = 0, prefixes = 0;
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for(;;)
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{
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insn.b1 = fetch_byte();
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prefixes++;
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switch(insn.b1) {
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case 0x40: // rex
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case 0x41:
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case 0x42:
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case 0x43:
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case 0x44:
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case 0x45:
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case 0x46:
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case 0x47:
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case 0x48:
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case 0x49:
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case 0x4A:
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case 0x4B:
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case 0x4C:
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case 0x4D:
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case 0x4E:
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case 0x4F:
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if (! is_64) break;
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rex_prefix = insn.b1;
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continue;
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case 0x26: // ES:
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case 0x2e: // CS:
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case 0x36: // SS:
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case 0x3e: // DS:
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if (! is_64) insn.seg_override = (insn.b1 >> 3) & 3;
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rex_prefix = 0;
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continue;
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case 0x64: // FS:
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case 0x65: // GS:
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insn.seg_override = insn.b1 & 0xf;
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rex_prefix = 0;
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continue;
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case 0x66: // operand size override
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if (!insn.os_64) insn.os_32 = !is_32;
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if (!sse_prefix) sse_prefix = SSE_PREFIX_66;
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rex_prefix = 0;
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continue;
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case 0x67: // address size override
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if (!is_64) insn.as_32 = !is_32;
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insn.as_64 = 0;
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rex_prefix = 0;
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continue;
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case 0xf0: // lock
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rex_prefix = 0;
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continue;
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case 0xf2: // repne
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case 0xf3: // rep
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sse_prefix = (insn.b1 & 0xf) ^ 1;
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rex_prefix = 0;
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continue;
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// no more prefixes
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default:
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break;
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}
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break;
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}
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if (insn.b1 == 0x0f)
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{
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insn.b1 = 0x100 | fetch_byte();
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}
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if (rex_prefix) {
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insn.extend8b = 1;
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if (rex_prefix & 0x8) {
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insn.os_64 = 1;
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insn.os_32 = 1;
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}
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if (rex_prefix & 0x4) insn.rex_r = 8;
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if (rex_prefix & 0x2) insn.rex_x = 8;
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if (rex_prefix & 0x1) insn.rex_b = 8;
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}
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const BxDisasmOpcodeTable_t *opcode_table, *entry;
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if (is_64) {
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if (insn.os_64)
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opcode_table = BxDisasmOpcodes64q;
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else if (insn.os_32)
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opcode_table = BxDisasmOpcodes64d;
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else
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opcode_table = BxDisasmOpcodes64w;
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} else {
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if (insn.os_32)
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opcode_table = BxDisasmOpcodes32;
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else
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opcode_table = BxDisasmOpcodes16;
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}
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entry = opcode_table + insn.b1;
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if ((insn.b1 & ~1) == 0xc4 && (is_64 || (peek_byte() & 0xc0) == 0xc0))
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{
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if (sse_prefix)
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dis_sprintf("(bad vex+rex prefix) ");
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if (rex_prefix)
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dis_sprintf("(bad vex+sse prefix) ");
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// decode 0xC4 or 0xC5 VEX prefix
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sse_prefix = decode_vex(&insn);
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if (insn.b1 < 256 || insn.b1 >= 1024)
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entry = &BxDisasmGroupSSE_ERR[0];
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else
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entry = BxDisasmOpcodesAVX + (insn.b1 - 256);
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}
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/*
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if (insn.b1== 0x62 && (is_64 || (peek_byte() & 0xc0) == 0xc0))
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{
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if (sse_prefix)
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dis_sprintf("(bad evex+rex prefix) ");
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if (rex_prefix)
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dis_sprintf("(bad evex+sse prefix) ");
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// decode 0x62 EVEX prefix
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sse_prefix = decode_evex(&insn);
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if (insn.b1 < 256 || insn.b1 >= 1024)
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entry = &BxDisasmGroupSSE_ERR[0];
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// else
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// entry = BxDisasmOpcodesEVEX + (insn.b1 - 256);
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}
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*/
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else if (insn.b1 == 0x8f && (is_64 || (peek_byte() & 0xc0) == 0xc0) && (peek_byte() & 0x8) == 0x8)
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{
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if (sse_prefix)
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dis_sprintf("(bad xop+rex prefix) ");
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if (rex_prefix)
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dis_sprintf("(bad xop+sse prefix) ");
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// decode 0x8F XOP prefix
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sse_prefix = decode_xop(&insn);
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if (insn.b1 >= 768 || sse_prefix != 0)
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entry = &BxDisasmGroupSSE_ERR[0];
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else
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entry = BxDisasmOpcodesXOP + insn.b1;
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}
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if (insn.b1 >= 512 || instruction_has_modrm[insn.b1] || insn.is_xop > 0)
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{
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// take 3rd byte for 3-byte opcode
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if (entry->Attr == _GRP3BOP) {
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entry = &(OPCODE_TABLE(entry)[fetch_byte()]);
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}
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decode_modrm(&insn);
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}
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int attr = entry->Attr;
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while(attr)
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{
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switch(attr) {
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case _GROUPN:
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entry = &(OPCODE_TABLE(entry)[insn.nnn & 7]);
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break;
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case _GRPSSE66:
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/* SSE opcode group with only prefix 0x66 allowed */
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sse_opcode = 1;
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if (sse_prefix != SSE_PREFIX_66)
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entry = &(BxDisasmGroupSSE_ERR[sse_prefix]);
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attr = 0;
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continue;
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case _GRPSSEF2:
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/* SSE opcode group with only prefix 0xF2 allowed */
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sse_opcode = 1;
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if (sse_prefix != SSE_PREFIX_F2)
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entry = &(BxDisasmGroupSSE_ERR[sse_prefix]);
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attr = 0;
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continue;
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case _GRPSSEF3:
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/* SSE opcode group with only prefix 0xF3 allowed */
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sse_opcode = 1;
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if (sse_prefix != SSE_PREFIX_F3)
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entry = &(BxDisasmGroupSSE_ERR[sse_prefix]);
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attr = 0;
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continue;
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case _GRPSSENONE:
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/* SSE opcode group with no prefix only allowed */
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sse_opcode = 1;
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if (sse_prefix != SSE_PREFIX_NONE)
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entry = &(BxDisasmGroupSSE_ERR[sse_prefix]);
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attr = 0;
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continue;
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case _GRPSSE:
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sse_opcode = 1;
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/* For SSE opcodes, look into another 4 entries table
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with the opcode prefixes (NONE, 0x66, 0xF2, 0xF3) */
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entry = &(OPCODE_TABLE(entry)[sse_prefix]);
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break;
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case _GRPSSE2:
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sse_opcode = 1;
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/* For SSE opcodes, look into another 2 entries table
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with the opcode prefixes (NONE, 0x66)
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SSE prefixes 0xF2 and 0xF3 are not allowed */
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if (sse_prefix > SSE_PREFIX_66)
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entry = &(BxDisasmGroupSSE_ERR[sse_prefix]);
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else
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entry = &(OPCODE_TABLE(entry)[sse_prefix]);
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break;
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case _SPLIT11B:
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entry = &(OPCODE_TABLE(entry)[insn.mod != 3]); /* REG/MEM */
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break;
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case _GRPRM:
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entry = &(OPCODE_TABLE(entry)[insn.rm & 7]);
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break;
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case _GRPFP:
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if(insn.mod != 3)
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{
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entry = &(OPCODE_TABLE(entry)[insn.nnn & 7]);
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} else {
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int index = (insn.b1-0xD8)*64 + (insn.modrm & 0x3f);
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entry = &(BxDisasmOpcodeInfoFP[index]);
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}
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break;
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case _GRP3DNOW:
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entry = &(BxDisasm3DNowGroup[fetch_byte()]);
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break;
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case _GRP64B:
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entry = &(OPCODE_TABLE(entry)[insn.os_64 ? 2 : insn.os_32]);
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if (sse_prefix == SSE_PREFIX_66)
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sse_prefix = 0;
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break;
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case _GRPVEXW:
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entry = &(OPCODE_TABLE(entry)[insn.vex_w]);
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break;
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default:
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printf("Internal disassembler error - unknown attribute !\n");
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return x86_insn(is_32, is_64);
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}
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/* get additional attributes from group table */
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attr = entry->Attr;
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}
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#define BRANCH_NOT_TAKEN 0x2E
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#define BRANCH_TAKEN 0x3E
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unsigned branch_hint = 0;
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// print prefixes
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for(unsigned i=0;i<prefixes;i++)
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{
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Bit8u prefix_byte = *(instr+i);
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if (prefix_byte == 0xF0) dis_sprintf("lock ");
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if (! insn.is_xop && ! insn.is_vex) {
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if (insn.b1 == 0x90 && !insn.rex_b && prefix_byte == 0xF3)
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continue;
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if (prefix_byte == 0xF3 || prefix_byte == 0xF2) {
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if (! sse_opcode) {
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const BxDisasmOpcodeTable_t *prefix = &(opcode_table[prefix_byte]);
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dis_sprintf("%s ", OPCODE(prefix)->IntelOpcode);
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}
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}
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// branch hint for jcc instructions
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if ((insn.b1 >= 0x070 && insn.b1 <= 0x07F) ||
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(insn.b1 >= 0x180 && insn.b1 <= 0x18F))
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{
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if (prefix_byte == BRANCH_NOT_TAKEN || prefix_byte == BRANCH_TAKEN)
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branch_hint = prefix_byte;
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}
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}
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}
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const BxDisasmOpcodeInfo_t *opcode = OPCODE(entry);
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if (! insn.is_xop && ! insn.is_vex) {
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// patch jecx opcode
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if (insn.b1 == 0xE3 && insn.as_32 && !insn.as_64)
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opcode = &Ia_jecxz_Jb;
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// fix nop opcode
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if (insn.b1 == 0x90) {
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if (sse_prefix == SSE_PREFIX_F3)
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opcode = &Ia_pause;
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else if (!insn.rex_b)
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opcode = &Ia_nop;
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}
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}
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// print instruction disassembly
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if (intel_mode)
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print_disassembly_intel(&insn, opcode);
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else
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print_disassembly_att (&insn, opcode);
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if (branch_hint == BRANCH_NOT_TAKEN)
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{
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dis_sprintf(", not taken");
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}
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else if (branch_hint == BRANCH_TAKEN)
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{
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dis_sprintf(", taken");
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}
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if (insn.is_vex < 0)
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dis_sprintf(" (bad vex)");
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else if (insn.is_evex < 0)
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dis_sprintf(" (bad evex)");
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else if (insn.is_xop < 0)
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dis_sprintf(" (bad xop)");
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insn.ilen = (unsigned)(instruction - instruction_begin);
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return insn;
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}
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unsigned disassembler::decode_vex(x86_insn *insn)
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{
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insn->is_vex = 1;
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unsigned b2 = fetch_byte(), vex_opcode_extension = 1;
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insn->rex_r = (b2 & 0x80) ? 0 : 0x8;
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if (insn->b1 == 0xc4) {
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// decode 3-byte VEX prefix
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insn->rex_x = (b2 & 0x40) ? 0 : 0x8;
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if (insn->is_64)
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insn->rex_b = (b2 & 0x20) ? 0 : 0x8;
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|
|
vex_opcode_extension = b2 & 0x1f;
|
|
if (! vex_opcode_extension || vex_opcode_extension > 3)
|
|
insn->is_vex = -1;
|
|
|
|
b2 = fetch_byte(); // fetch VEX3 byte
|
|
if (b2 & 0x80) {
|
|
insn->os_64 = 1;
|
|
insn->os_32 = 1;
|
|
insn->vex_w = 1;
|
|
}
|
|
}
|
|
|
|
insn->vex_vvv = 15 - ((b2 >> 3) & 0xf);
|
|
if (! insn->is_64) insn->vex_vvv &= 7;
|
|
insn->vex_l = (b2 >> 2) & 0x1;
|
|
insn->b1 = fetch_byte() + 256 * vex_opcode_extension;
|
|
return b2 & 0x3;
|
|
}
|
|
|
|
unsigned disassembler::decode_evex(x86_insn *insn)
|
|
{
|
|
insn->is_evex = 1;
|
|
|
|
Bit32u evex = fetch_dword();
|
|
|
|
// check for reserved EVEX bits
|
|
if ((evex & 0x0c) != 0 || (evex & 0x400) == 0) {
|
|
insn->is_evex = -1;
|
|
}
|
|
|
|
unsigned evex_opcext = evex & 0x3;
|
|
if (evex_opcext == 0) {
|
|
insn->is_evex = -1;
|
|
}
|
|
|
|
if (insn->is_64) {
|
|
insn->rex_r = ((evex >> 4) & 0x8) ^ 0x8;
|
|
insn->rex_r |= (evex & 0x10) ^ 0x10;
|
|
insn->rex_x = ((evex >> 3) & 0x8) ^ 0x8;
|
|
insn->rex_b = ((evex >> 2) & 0x8) ^ 0x8;
|
|
insn->rex_b |= (insn->rex_x << 1);
|
|
}
|
|
|
|
unsigned sse_prefix = (evex >> 8) & 0x3;
|
|
|
|
insn->vex_vvv = 15 - ((evex >> 11) & 0xf);
|
|
unsigned evex_v = ((evex >> 15) & 0x10) ^ 0x10;
|
|
insn->vex_vvv |= evex_v;
|
|
if (! insn->is_64) insn->vex_vvv &= 7;
|
|
|
|
insn->vex_w = (evex >> 15) & 0x1;
|
|
if (insn->vex_w) {
|
|
insn->os_64 = 1;
|
|
insn->os_32 = 1;
|
|
}
|
|
|
|
insn->evex_b = (evex >> 20) & 0x1;
|
|
insn->evex_ll_rc = (evex >> 21) & 0x3;
|
|
insn->evex_z = (evex >> 23) & 0x1;
|
|
|
|
insn->b1 = (evex >> 24);
|
|
insn->b1 += 256 * (evex_opcext-1);
|
|
|
|
return sse_prefix;
|
|
}
|
|
|
|
unsigned disassembler::decode_xop(x86_insn *insn)
|
|
{
|
|
insn->is_xop = 1;
|
|
|
|
unsigned b2 = fetch_byte();
|
|
|
|
insn->rex_r = (b2 & 0x80) ? 0 : 0x8;
|
|
insn->rex_x = (b2 & 0x40) ? 0 : 0x8;
|
|
if (insn->is_64)
|
|
insn->rex_b = (b2 & 0x20) ? 0 : 0x8;
|
|
|
|
unsigned xop_opcode_extension = (b2 & 0x1f) - 8;
|
|
if (xop_opcode_extension >= 3)
|
|
insn->is_xop = -1;
|
|
|
|
b2 = fetch_byte(); // fetch VEX3 byte
|
|
if (b2 & 0x80) {
|
|
insn->os_64 = 1;
|
|
insn->os_32 = 1;
|
|
insn->vex_w = 1;
|
|
}
|
|
|
|
insn->vex_vvv = 15 - ((b2 >> 3) & 0xf);
|
|
if (! insn->is_64) insn->vex_vvv &= 7;
|
|
insn->vex_l = (b2 >> 2) & 0x1;
|
|
insn->b1 = fetch_byte() + 256 * xop_opcode_extension;
|
|
|
|
return b2 & 0x3;
|
|
}
|
|
|
|
void disassembler::dis_sprintf(const char *fmt, ...)
|
|
{
|
|
va_list ap;
|
|
|
|
va_start(ap, fmt);
|
|
vsprintf(disbufptr, fmt, ap);
|
|
va_end(ap);
|
|
|
|
disbufptr += strlen(disbufptr);
|
|
}
|
|
|
|
void disassembler::dis_putc(char symbol)
|
|
{
|
|
*disbufptr++ = symbol;
|
|
*disbufptr = 0;
|
|
}
|