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https://github.com/dolphin-emu/dolphin.git
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775dc8a9c0
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4 8ced0084-cf51-0410-be5f-012b33b47a6e
329 lines
8.6 KiB
C++
329 lines
8.6 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: dis_decode.cc,v 1.32 2006/05/12 17:04:19 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include "disasm.h"
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#include "dis_tables.h"
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#define OPCODE(entry) ((BxDisasmOpcodeInfo_t*) entry->OpcodeInfo)
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#define OPCODE_TABLE(entry) ((BxDisasmOpcodeTable_t*) entry->OpcodeInfo)
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#ifndef NULL
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#define NULL 0
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#endif
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static const unsigned char instruction_has_modrm[512] = {
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/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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/* ------------------------------- */
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/* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
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/* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
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/* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
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/* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,
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/* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0,
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/* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
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/* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* A0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* B0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* C0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0,
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/* D0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1,
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/* E0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
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/* F0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1,
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/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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/* ------------------------------- */
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1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0F 00 */
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1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 0F 10 */
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1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,1, /* 0F 20 */
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0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 0F 30 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 40 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 50 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 60 */
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1,1,1,1,1,1,1,0,0,0,0,0,1,1,1,1, /* 0F 70 */
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0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0F 80 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F 90 */
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0,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1, /* 0F A0 */
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1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1, /* 0F B0 */
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1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 0F C0 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F D0 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 0F E0 */
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1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* 0F F0 */
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/* ------------------------------- */
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/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
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};
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unsigned disassembler::disasm(bx_bool is_32, bx_bool is_64, bx_address base, bx_address ip, const Bit8u *instr, char *disbuf)
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{
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x86_insn insn = decode(is_32, is_64, base, ip, instr, disbuf);
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return insn.ilen;
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}
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x86_insn disassembler::decode(bx_bool is_32, bx_bool is_64, bx_address base, bx_address ip, const Bit8u *instr, char *disbuf)
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{
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x86_insn insn(is_32, is_64);
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const Bit8u *instruction_begin = instruction = instr;
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resolve_modrm = NULL;
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unsigned b3 = 0;
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db_eip = ip;
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db_base = base; // cs linear base (base for PM & cs<<4 for RM & VM)
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disbufptr = disbuf; // start sprintf()'ing into beginning of buffer
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#define SSE_PREFIX_NONE 0
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#define SSE_PREFIX_66 1
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#define SSE_PREFIX_F2 2
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#define SSE_PREFIX_F3 3 /* only one SSE prefix could be used */
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unsigned sse_prefix = SSE_PREFIX_NONE;
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for(;;)
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{
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insn.b1 = fetch_byte();
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insn.prefixes++;
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switch(insn.b1) {
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case 0x40: // rex
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case 0x41:
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case 0x42:
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case 0x43:
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case 0x44:
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case 0x45:
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case 0x46:
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case 0x47:
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case 0x48:
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case 0x49:
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case 0x4A:
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case 0x4B:
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case 0x4C:
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case 0x4D:
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case 0x4E:
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case 0x4F:
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if (! is_64) break;
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insn.extend8b = 1;
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if (insn.b1 & 0x8) {
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insn.os_64 = 1;
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insn.os_32 = 1;
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}
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if (insn.b1 & 0x4) insn.rex_r = 8;
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if (insn.b1 & 0x2) insn.rex_x = 8;
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if (insn.b1 & 0x1) insn.rex_b = 8;
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continue;
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case 0x26: // ES:
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if (! is_64) insn.seg_override = ES_REG;
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continue;
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case 0x2e: // CS:
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if (! is_64) insn.seg_override = CS_REG;
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continue;
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case 0x36: // SS:
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if (! is_64) insn.seg_override = SS_REG;
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continue;
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case 0x3e: // DS:
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if (! is_64) insn.seg_override = DS_REG;
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continue;
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case 0x64: // FS:
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insn.seg_override = FS_REG;
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continue;
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case 0x65: // GS:
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insn.seg_override = GS_REG;
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continue;
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case 0x66: // operand size override
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if (!insn.os_64) insn.os_32 = !is_32;
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if (!sse_prefix) sse_prefix = SSE_PREFIX_66;
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continue;
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case 0x67: // address size override
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if (!is_64) insn.as_32 = !is_32;
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insn.as_64 = 0;
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continue;
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case 0xf0: // lock
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continue;
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case 0xf2: // repne
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if (!sse_prefix) sse_prefix = SSE_PREFIX_F2;
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continue;
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case 0xf3: // rep
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if (!sse_prefix) sse_prefix = SSE_PREFIX_F3;
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continue;
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// no more prefixes
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default:
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break;
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}
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insn.prefixes--;
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break;
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}
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if (insn.b1 == 0x0f)
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{
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insn.b1 = 0x100 | fetch_byte();
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}
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const BxDisasmOpcodeTable_t *opcode_table, *entry;
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if (is_64) {
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if (insn.os_64)
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opcode_table = BxDisasmOpcodes64q;
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else if (insn.os_32)
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opcode_table = BxDisasmOpcodes64d;
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else
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opcode_table = BxDisasmOpcodes64w;
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} else {
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if (insn.os_32)
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opcode_table = BxDisasmOpcodes32;
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else
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opcode_table = BxDisasmOpcodes16;
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}
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entry = opcode_table + insn.b1;
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// will require 3rd byte for 3-byte opcode
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if (entry->Attr & _GRP3BTAB) b3 = fetch_byte();
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if (instruction_has_modrm[insn.b1])
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{
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decode_modrm(&insn);
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}
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int attr = entry->Attr;
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while(attr)
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{
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switch(attr) {
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case _GROUPN:
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entry = &(OPCODE_TABLE(entry)[insn.nnn]);
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break;
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case _GRPSSE:
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if(sse_prefix) insn.prefixes--;
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/* For SSE opcodes, look into another 4 entries table
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with the opcode prefixes (NONE, 0x66, 0xF2, 0xF3) */
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entry = &(OPCODE_TABLE(entry)[sse_prefix]);
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break;
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case _SPLIT11B:
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entry = &(OPCODE_TABLE(entry)[insn.mod != 3]); /* REG/MEM */
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break;
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case _GRPRM:
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entry = &(OPCODE_TABLE(entry)[insn.rm]);
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break;
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case _GRPFP:
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if(insn.mod != 3)
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{
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entry = &(OPCODE_TABLE(entry)[insn.nnn]);
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} else {
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int index = (insn.b1-0xD8)*64 + (insn.modrm & 0x3f);
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entry = &(BxDisasmOpcodeInfoFP[index]);
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}
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break;
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case _GRP3DNOW:
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entry = &(BxDisasm3DNowGroup[peek_byte()]);
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break;
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case _GRP3BTAB:
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entry = &(OPCODE_TABLE(entry)[b3 >> 4]);
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break;
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case _GRP3BOP:
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entry = &(OPCODE_TABLE(entry)[b3 & 15]);
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break;
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default:
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printf("Internal disassembler error - unknown attribute !\n");
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return x86_insn(is_32, is_64);
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}
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/* get additional attributes from group table */
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attr = entry->Attr;
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}
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#define BRANCH_NOT_TAKEN 0x2E
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#define BRANCH_TAKEN 0x3E
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unsigned branch_hint = 0;
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// print prefixes
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for(unsigned i=0;i<insn.prefixes;i++)
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{
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Bit8u prefix_byte = *(instr+i);
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if (prefix_byte == 0xF3 || prefix_byte == 0xF2 || prefix_byte == 0xF0)
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{
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const BxDisasmOpcodeTable_t *prefix = &(opcode_table[prefix_byte]);
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dis_sprintf("%s ", OPCODE(prefix)->IntelOpcode);
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}
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// branch hint for jcc instructions
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if ((insn.b1 >= 0x070 && insn.b1 <= 0x07F) ||
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(insn.b1 >= 0x180 && insn.b1 <= 0x18F))
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{
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if (prefix_byte == BRANCH_NOT_TAKEN || prefix_byte == BRANCH_TAKEN)
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branch_hint = prefix_byte;
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}
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}
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const BxDisasmOpcodeInfo_t *opcode = OPCODE(entry);
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// patch jecx opcode
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if (insn.b1 == 0xE3 && insn.as_32 && !insn.as_64)
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opcode = &Ia_jecxz_Jb;
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// fix nop opcode
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if (insn.b1 == 0x90 && !insn.rex_b) {
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opcode = &Ia_nop;
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}
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// print instruction disassembly
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if (intel_mode)
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print_disassembly_intel(&insn, opcode);
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else
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print_disassembly_att (&insn, opcode);
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if (branch_hint == BRANCH_NOT_TAKEN)
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{
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dis_sprintf(", not taken");
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}
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else if (branch_hint == BRANCH_TAKEN)
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{
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dis_sprintf(", taken");
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}
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insn.ilen = (unsigned)(instruction - instruction_begin);
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return insn;
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}
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void disassembler::dis_sprintf(const char *fmt, ...)
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{
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va_list ap;
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va_start(ap, fmt);
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vsprintf(disbufptr, fmt, ap);
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va_end(ap);
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disbufptr += strlen(disbufptr);
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}
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void disassembler::dis_putc(char symbol)
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{
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*disbufptr++ = symbol;
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*disbufptr = 0;
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}
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