mirror of
https://github.com/dolphin-emu/dolphin.git
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8da425b008
Block braces on new lines. Also killed off trailing whitespace and dangling elses. Spaced some things out to make them more readable (only in places where it looked like a bit of a clusterfuck).
705 lines
21 KiB
C++
705 lines
21 KiB
C++
// Copyright 2013 Dolphin Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#include "Common.h"
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#include "VideoCommon.h"
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#include "VideoConfig.h"
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#include "MathUtil.h"
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#include "Thread.h"
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#include "Atomic.h"
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#include "OpcodeDecoding.h"
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#include "Fifo.h"
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#include "ChunkFile.h"
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#include "CommandProcessor.h"
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#include "PixelEngine.h"
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#include "CoreTiming.h"
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#include "ConfigManager.h"
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#include "HW/ProcessorInterface.h"
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#include "HW/GPFifo.h"
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#include "HW/Memmap.h"
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#include "DLCache.h"
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#include "HW/SystemTimers.h"
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#include "Core.h"
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namespace CommandProcessor
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{
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int et_UpdateInterrupts;
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// TODO(ector): Warn on bbox read/write
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// STATE_TO_SAVE
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SCPFifoStruct fifo;
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UCPStatusReg m_CPStatusReg;
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UCPCtrlReg m_CPCtrlReg;
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UCPClearReg m_CPClearReg;
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int m_bboxleft;
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int m_bboxtop;
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int m_bboxright;
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int m_bboxbottom;
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u16 m_tokenReg;
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static bool bProcessFifoToLoWatermark = false;
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static bool bProcessFifoAllDistance = false;
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volatile bool isPossibleWaitingSetDrawDone = false;
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volatile bool isHiWatermarkActive = false;
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volatile bool isLoWatermarkActive = false;
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volatile bool interruptSet= false;
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volatile bool interruptWaiting= false;
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volatile bool interruptTokenWaiting = false;
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volatile bool interruptFinishWaiting = false;
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volatile bool waitingForPEInterruptDisable = false;
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volatile u32 VITicks = CommandProcessor::m_cpClockOrigin;
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bool IsOnThread()
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{
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return SConfig::GetInstance().m_LocalCoreStartupParameter.bCPUThread;
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}
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void UpdateInterrupts_Wrapper(u64 userdata, int cyclesLate)
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{
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UpdateInterrupts(userdata);
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}
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void DoState(PointerWrap &p)
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{
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p.DoPOD(m_CPStatusReg);
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p.DoPOD(m_CPCtrlReg);
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p.DoPOD(m_CPClearReg);
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p.Do(m_bboxleft);
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p.Do(m_bboxtop);
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p.Do(m_bboxright);
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p.Do(m_bboxbottom);
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p.Do(m_tokenReg);
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p.Do(fifo);
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p.Do(bProcessFifoToLoWatermark);
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p.Do(bProcessFifoAllDistance);
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p.Do(isHiWatermarkActive);
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p.Do(isLoWatermarkActive);
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p.Do(isPossibleWaitingSetDrawDone);
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p.Do(interruptSet);
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p.Do(interruptWaiting);
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p.Do(interruptTokenWaiting);
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p.Do(interruptFinishWaiting);
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}
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inline void WriteLow (volatile u32& _reg, u16 lowbits) {Common::AtomicStore(_reg,(_reg & 0xFFFF0000) | lowbits);}
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inline void WriteHigh(volatile u32& _reg, u16 highbits) {Common::AtomicStore(_reg,(_reg & 0x0000FFFF) | ((u32)highbits << 16));}
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inline u16 ReadLow (u32 _reg) {return (u16)(_reg & 0xFFFF);}
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inline u16 ReadHigh (u32 _reg) {return (u16)(_reg >> 16);}
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void Init()
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{
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m_CPStatusReg.Hex = 0;
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m_CPStatusReg.CommandIdle = 1;
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m_CPStatusReg.ReadIdle = 1;
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m_CPCtrlReg.Hex = 0;
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m_CPClearReg.Hex = 0;
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m_bboxleft = 0;
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m_bboxtop = 0;
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m_bboxright = 640;
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m_bboxbottom = 480;
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m_tokenReg = 0;
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memset(&fifo,0,sizeof(fifo));
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fifo.CPCmdIdle = 1;
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fifo.CPReadIdle = 1;
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fifo.bFF_Breakpoint = 0;
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fifo.bFF_HiWatermark = 0;
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fifo.bFF_HiWatermarkInt = 0;
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fifo.bFF_LoWatermark = 0;
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fifo.bFF_LoWatermarkInt = 0;
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interruptSet = false;
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interruptWaiting = false;
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interruptFinishWaiting = false;
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interruptTokenWaiting = false;
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bProcessFifoToLoWatermark = false;
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bProcessFifoAllDistance = false;
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isPossibleWaitingSetDrawDone = false;
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isHiWatermarkActive = false;
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isLoWatermarkActive = false;
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et_UpdateInterrupts = CoreTiming::RegisterEvent("CPInterrupt", UpdateInterrupts_Wrapper);
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}
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void Read16(u16& _rReturnValue, const u32 _Address)
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{
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INFO_LOG(COMMANDPROCESSOR, "(r): 0x%08x", _Address);
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switch (_Address & 0xFFF)
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{
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case STATUS_REGISTER:
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SetCpStatusRegister();
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_rReturnValue = m_CPStatusReg.Hex;
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return;
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case CTRL_REGISTER: _rReturnValue = m_CPCtrlReg.Hex; return;
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case CLEAR_REGISTER:
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_rReturnValue = m_CPClearReg.Hex;
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PanicAlert("CommandProcessor:: CPU reads from CLEAR_REGISTER!");
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ERROR_LOG(COMMANDPROCESSOR, "(r) clear: 0x%04x", _rReturnValue);
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return;
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case FIFO_TOKEN_REGISTER: _rReturnValue = m_tokenReg; return;
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case FIFO_BOUNDING_BOX_LEFT: _rReturnValue = m_bboxleft; return;
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case FIFO_BOUNDING_BOX_RIGHT: _rReturnValue = m_bboxright; return;
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case FIFO_BOUNDING_BOX_TOP: _rReturnValue = m_bboxtop; return;
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case FIFO_BOUNDING_BOX_BOTTOM: _rReturnValue = m_bboxbottom; return;
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case FIFO_BASE_LO: _rReturnValue = ReadLow (fifo.CPBase); return;
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case FIFO_BASE_HI: _rReturnValue = ReadHigh(fifo.CPBase); return;
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case FIFO_END_LO: _rReturnValue = ReadLow (fifo.CPEnd); return;
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case FIFO_END_HI: _rReturnValue = ReadHigh(fifo.CPEnd); return;
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case FIFO_HI_WATERMARK_LO: _rReturnValue = ReadLow (fifo.CPHiWatermark); return;
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case FIFO_HI_WATERMARK_HI: _rReturnValue = ReadHigh(fifo.CPHiWatermark); return;
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case FIFO_LO_WATERMARK_LO: _rReturnValue = ReadLow (fifo.CPLoWatermark); return;
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case FIFO_LO_WATERMARK_HI: _rReturnValue = ReadHigh(fifo.CPLoWatermark); return;
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case FIFO_RW_DISTANCE_LO:
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if (IsOnThread())
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{
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if(fifo.CPWritePointer >= fifo.SafeCPReadPointer)
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_rReturnValue = ReadLow (fifo.CPWritePointer - fifo.SafeCPReadPointer);
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else
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_rReturnValue = ReadLow (fifo.CPEnd - fifo.SafeCPReadPointer + fifo.CPWritePointer - fifo.CPBase + 32);
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}
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else
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{
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_rReturnValue = ReadLow (fifo.CPReadWriteDistance);
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}
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DEBUG_LOG(COMMANDPROCESSOR, "Read FIFO_RW_DISTANCE_LO : %04x", _rReturnValue);
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return;
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case FIFO_RW_DISTANCE_HI:
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if (IsOnThread())
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{
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if(fifo.CPWritePointer >= fifo.SafeCPReadPointer)
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_rReturnValue = ReadHigh (fifo.CPWritePointer - fifo.SafeCPReadPointer);
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else
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_rReturnValue = ReadHigh (fifo.CPEnd - fifo.SafeCPReadPointer + fifo.CPWritePointer - fifo.CPBase + 32);
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}
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else
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{
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_rReturnValue = ReadHigh(fifo.CPReadWriteDistance);
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}
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DEBUG_LOG(COMMANDPROCESSOR, "Read FIFO_RW_DISTANCE_HI : %04x", _rReturnValue);
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return;
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case FIFO_WRITE_POINTER_LO:
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_rReturnValue = ReadLow (fifo.CPWritePointer);
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DEBUG_LOG(COMMANDPROCESSOR, "Read FIFO_WRITE_POINTER_LO : %04x", _rReturnValue);
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return;
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case FIFO_WRITE_POINTER_HI:
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_rReturnValue = ReadHigh(fifo.CPWritePointer);
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DEBUG_LOG(COMMANDPROCESSOR, "Read FIFO_WRITE_POINTER_HI : %04x", _rReturnValue);
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return;
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case FIFO_READ_POINTER_LO:
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if (IsOnThread())
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_rReturnValue = ReadLow (fifo.SafeCPReadPointer);
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else
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_rReturnValue = ReadLow (fifo.CPReadPointer);
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DEBUG_LOG(COMMANDPROCESSOR, "Read FIFO_READ_POINTER_LO : %04x", _rReturnValue);
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return;
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case FIFO_READ_POINTER_HI:
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if (IsOnThread())
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_rReturnValue = ReadHigh (fifo.SafeCPReadPointer);
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else
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_rReturnValue = ReadHigh (fifo.CPReadPointer);
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DEBUG_LOG(COMMANDPROCESSOR, "Read FIFO_READ_POINTER_HI : %04x", _rReturnValue);
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return;
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case FIFO_BP_LO: _rReturnValue = ReadLow (fifo.CPBreakpoint); return;
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case FIFO_BP_HI: _rReturnValue = ReadHigh(fifo.CPBreakpoint); return;
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case XF_RASBUSY_L:
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_rReturnValue = 0; // TODO: Figure out the true value
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DEBUG_LOG(COMMANDPROCESSOR, "Read from XF_RASBUSY_L: %04x", _rReturnValue);
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return;
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case XF_RASBUSY_H:
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_rReturnValue = 0; // TODO: Figure out the true value
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DEBUG_LOG(COMMANDPROCESSOR, "Read from XF_RASBUSY_H: %04x", _rReturnValue);
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return;
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case XF_CLKS_L:
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_rReturnValue = 0; // TODO: Figure out the true value
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DEBUG_LOG(COMMANDPROCESSOR, "Read from XF_CLKS_L: %04x", _rReturnValue);
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return;
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case XF_CLKS_H:
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_rReturnValue = 0; // TODO: Figure out the true value
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DEBUG_LOG(COMMANDPROCESSOR, "Read from XF_CLKS_H: %04x", _rReturnValue);
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return;
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case XF_WAIT_IN_L:
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_rReturnValue = 0; // TODO: Figure out the true value
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DEBUG_LOG(COMMANDPROCESSOR, "Read from XF_WAIT_IN_L: %04x", _rReturnValue);
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return;
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case XF_WAIT_IN_H:
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_rReturnValue = 0; // TODO: Figure out the true value
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DEBUG_LOG(COMMANDPROCESSOR, "Read from XF_WAIT_IN_H: %04x", _rReturnValue);
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return;
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case XF_WAIT_OUT_L:
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_rReturnValue = 0; // TODO: Figure out the true value
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DEBUG_LOG(COMMANDPROCESSOR, "Read from XF_WAIT_OUT_L: %04x", _rReturnValue);
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return;
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case XF_WAIT_OUT_H:
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_rReturnValue = 0; // TODO: Figure out the true value
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DEBUG_LOG(COMMANDPROCESSOR, "Read from XF_WAIT_OUT_H: %04x", _rReturnValue);
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return;
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case VCACHE_METRIC_CHECK_L:
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_rReturnValue = 0; // TODO: Figure out the true value
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DEBUG_LOG(COMMANDPROCESSOR, "Read from VCACHE_METRIC_CHECK_L: %04x", _rReturnValue);
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return;
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case VCACHE_METRIC_CHECK_H:
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_rReturnValue = 0; // TODO: Figure out the true value
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DEBUG_LOG(COMMANDPROCESSOR, "Read from VCACHE_METRIC_CHECK_H: %04x", _rReturnValue);
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return;
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case VCACHE_METRIC_MISS_L:
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_rReturnValue = 0; // TODO: Figure out the true value
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DEBUG_LOG(COMMANDPROCESSOR, "Read from VCACHE_METRIC_MISS_L: %04x", _rReturnValue);
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return;
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case VCACHE_METRIC_MISS_H:
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_rReturnValue = 0; // TODO: Figure out the true value
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DEBUG_LOG(COMMANDPROCESSOR, "Read from VCACHE_METRIC_MISS_H: %04x", _rReturnValue);
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return;
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case VCACHE_METRIC_STALL_L:
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_rReturnValue = 0; // TODO: Figure out the true value
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DEBUG_LOG(COMMANDPROCESSOR, "Read from VCACHE_METRIC_STALL_L: %04x", _rReturnValue);
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return;
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case VCACHE_METRIC_STALL_H:
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_rReturnValue = 0; // TODO: Figure out the true value
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DEBUG_LOG(COMMANDPROCESSOR, "Read from VCACHE_METRIC_STALL_H: %04x", _rReturnValue);
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return;
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case CLKS_PER_VTX_OUT:
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_rReturnValue = 4; //Number of clocks per vertex.. TODO: Calculate properly
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DEBUG_LOG(COMMANDPROCESSOR, "Read from CLKS_PER_VTX_OUT: %04x", _rReturnValue);
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return;
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default:
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_rReturnValue = 0;
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WARN_LOG(COMMANDPROCESSOR, "(r16) unknown CP reg @ %08x", _Address);
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return;
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}
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return;
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}
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void Write16(const u16 _Value, const u32 _Address)
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{
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INFO_LOG(COMMANDPROCESSOR, "(write16): 0x%04x @ 0x%08x",_Value,_Address);
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switch (_Address & 0xFFF)
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{
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case STATUS_REGISTER:
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{
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// This should be Read-Only
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ERROR_LOG(COMMANDPROCESSOR,"\t write to STATUS_REGISTER : %04x", _Value);
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PanicAlert("CommandProcessor:: CPU writes to STATUS_REGISTER!");
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}
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break;
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case CTRL_REGISTER:
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{
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UCPCtrlReg tmpCtrl(_Value);
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m_CPCtrlReg.Hex = tmpCtrl.Hex;
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INFO_LOG(COMMANDPROCESSOR,"\t Write to CTRL_REGISTER : %04x", _Value);
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SetCpControlRegister();
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}
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break;
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case CLEAR_REGISTER:
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{
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UCPClearReg tmpCtrl(_Value);
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m_CPClearReg.Hex = tmpCtrl.Hex;
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DEBUG_LOG(COMMANDPROCESSOR,"\t Write to CLEAR_REGISTER : %04x", _Value);
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SetCpClearRegister();
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}
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break;
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case PERF_SELECT:
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// Seems to select which set of perf registers should be exposed.
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DEBUG_LOG(COMMANDPROCESSOR, "Write to PERF_SELECT: %04x", _Value);
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break;
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// Fifo Registers
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case FIFO_TOKEN_REGISTER:
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m_tokenReg = _Value;
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DEBUG_LOG(COMMANDPROCESSOR,"\t Write to FIFO_TOKEN_REGISTER : %04x", _Value);
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break;
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case FIFO_BASE_LO:
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WriteLow ((u32 &)fifo.CPBase, _Value & 0xFFE0);
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DEBUG_LOG(COMMANDPROCESSOR,"\t Write to FIFO_BASE_LO : %04x", _Value);
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break;
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case FIFO_BASE_HI:
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WriteHigh((u32 &)fifo.CPBase, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t Write to FIFO_BASE_HI : %04x", _Value);
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break;
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case FIFO_END_LO:
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WriteLow ((u32 &)fifo.CPEnd, _Value & 0xFFE0);
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DEBUG_LOG(COMMANDPROCESSOR,"\t Write to FIFO_END_LO : %04x", _Value);
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break;
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case FIFO_END_HI:
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WriteHigh((u32 &)fifo.CPEnd, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t Write to FIFO_END_HI : %04x", _Value);
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break;
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case FIFO_WRITE_POINTER_LO:
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WriteLow ((u32 &)fifo.CPWritePointer, _Value & 0xFFE0);
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DEBUG_LOG(COMMANDPROCESSOR,"\t Write to FIFO_WRITE_POINTER_LO : %04x", _Value);
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break;
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case FIFO_WRITE_POINTER_HI:
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WriteHigh((u32 &)fifo.CPWritePointer, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t Write to FIFO_WRITE_POINTER_HI : %04x", _Value);
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break;
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case FIFO_READ_POINTER_LO:
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WriteLow ((u32 &)fifo.CPReadPointer, _Value & 0xFFE0);
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DEBUG_LOG(COMMANDPROCESSOR,"\t Write to FIFO_READ_POINTER_LO : %04x", _Value);
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break;
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case FIFO_READ_POINTER_HI:
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WriteHigh((u32 &)fifo.CPReadPointer, _Value);
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fifo.SafeCPReadPointer = fifo.CPReadPointer;
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DEBUG_LOG(COMMANDPROCESSOR,"\t Write to FIFO_READ_POINTER_HI : %04x", _Value);
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break;
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case FIFO_HI_WATERMARK_LO:
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WriteLow ((u32 &)fifo.CPHiWatermark, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t Write to FIFO_HI_WATERMARK_LO : %04x", _Value);
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break;
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case FIFO_HI_WATERMARK_HI:
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WriteHigh((u32 &)fifo.CPHiWatermark, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t Write to FIFO_HI_WATERMARK_HI : %04x", _Value);
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break;
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case FIFO_LO_WATERMARK_LO:
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WriteLow ((u32 &)fifo.CPLoWatermark, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t Write to FIFO_LO_WATERMARK_LO : %04x", _Value);
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break;
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case FIFO_LO_WATERMARK_HI:
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WriteHigh((u32 &)fifo.CPLoWatermark, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t Write to FIFO_LO_WATERMARK_HI : %04x", _Value);
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break;
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case FIFO_BP_LO:
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WriteLow ((u32 &)fifo.CPBreakpoint, _Value & 0xFFE0);
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DEBUG_LOG(COMMANDPROCESSOR,"Write to FIFO_BP_LO : %04x", _Value);
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break;
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case FIFO_BP_HI:
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WriteHigh((u32 &)fifo.CPBreakpoint, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"Write to FIFO_BP_HI : %04x", _Value);
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break;
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case FIFO_RW_DISTANCE_HI:
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WriteHigh((u32 &)fifo.CPReadWriteDistance, _Value);
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if (fifo.CPReadWriteDistance == 0)
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{
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GPFifo::ResetGatherPipe();
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ResetVideoBuffer();
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}
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else
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{
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ResetVideoBuffer();
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}
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IncrementCheckContextId();
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DEBUG_LOG(COMMANDPROCESSOR,"Try to write to FIFO_RW_DISTANCE_HI : %04x", _Value);
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break;
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case FIFO_RW_DISTANCE_LO:
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WriteLow((u32 &)fifo.CPReadWriteDistance, _Value & 0xFFE0);
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DEBUG_LOG(COMMANDPROCESSOR,"Try to write to FIFO_RW_DISTANCE_LO : %04x", _Value);
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break;
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default:
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WARN_LOG(COMMANDPROCESSOR, "(w16) unknown CP reg write %04x @ %08x", _Value, _Address);
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}
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if (!IsOnThread())
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RunGpu();
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}
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void Read32(u32& _rReturnValue, const u32 _Address)
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{
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_rReturnValue = 0;
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_dbg_assert_msg_(COMMANDPROCESSOR, 0, "Read32 from CommandProccessor at 0x%08x", _Address);
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|
}
|
|
|
|
void Write32(const u32 _Data, const u32 _Address)
|
|
{
|
|
_dbg_assert_msg_(COMMANDPROCESSOR, 0, "Write32 at CommandProccessor at 0x%08x", _Address);
|
|
}
|
|
|
|
void STACKALIGN GatherPipeBursted()
|
|
{
|
|
ProcessFifoEvents();
|
|
// if we aren't linked, we don't care about gather pipe data
|
|
if (!m_CPCtrlReg.GPLinkEnable)
|
|
{
|
|
if (!IsOnThread())
|
|
{
|
|
RunGpu();
|
|
}
|
|
else
|
|
{
|
|
// In multibuffer mode is not allowed write in the same FIFO attached to the GPU.
|
|
// Fix Pokemon XD in DC mode.
|
|
if((ProcessorInterface::Fifo_CPUEnd == fifo.CPEnd) && (ProcessorInterface::Fifo_CPUBase == fifo.CPBase)
|
|
&& fifo.CPReadWriteDistance > 0)
|
|
{
|
|
waitingForPEInterruptDisable = true;
|
|
ProcessFifoAllDistance();
|
|
waitingForPEInterruptDisable = false;
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
|
|
if (IsOnThread())
|
|
SetCpStatus(true);
|
|
|
|
// update the fifo pointer
|
|
if (fifo.CPWritePointer >= fifo.CPEnd)
|
|
fifo.CPWritePointer = fifo.CPBase;
|
|
else
|
|
fifo.CPWritePointer += GATHER_PIPE_SIZE;
|
|
|
|
Common::AtomicAdd(fifo.CPReadWriteDistance, GATHER_PIPE_SIZE);
|
|
|
|
if (!IsOnThread())
|
|
RunGpu();
|
|
|
|
_assert_msg_(COMMANDPROCESSOR, fifo.CPReadWriteDistance <= fifo.CPEnd - fifo.CPBase,
|
|
"FIFO is overflowed by GatherPipe !\nCPU thread is too fast!");
|
|
|
|
// check if we are in sync
|
|
_assert_msg_(COMMANDPROCESSOR, fifo.CPWritePointer == ProcessorInterface::Fifo_CPUWritePointer, "FIFOs linked but out of sync");
|
|
_assert_msg_(COMMANDPROCESSOR, fifo.CPBase == ProcessorInterface::Fifo_CPUBase, "FIFOs linked but out of sync");
|
|
_assert_msg_(COMMANDPROCESSOR, fifo.CPEnd == ProcessorInterface::Fifo_CPUEnd, "FIFOs linked but out of sync");
|
|
}
|
|
|
|
void UpdateInterrupts(u64 userdata)
|
|
{
|
|
if (userdata)
|
|
{
|
|
interruptSet = true;
|
|
INFO_LOG(COMMANDPROCESSOR,"Interrupt set");
|
|
ProcessorInterface::SetInterrupt(INT_CAUSE_CP, true);
|
|
}
|
|
else
|
|
{
|
|
interruptSet = false;
|
|
INFO_LOG(COMMANDPROCESSOR,"Interrupt cleared");
|
|
ProcessorInterface::SetInterrupt(INT_CAUSE_CP, false);
|
|
}
|
|
interruptWaiting = false;
|
|
}
|
|
|
|
void UpdateInterruptsFromVideoBackend(u64 userdata)
|
|
{
|
|
CoreTiming::ScheduleEvent_Threadsafe(0, et_UpdateInterrupts, userdata);
|
|
}
|
|
|
|
// This is called by the ProcessorInterface when PI_FIFO_RESET is written to.
|
|
void AbortFrame()
|
|
{
|
|
|
|
}
|
|
|
|
void SetCpStatus(bool isCPUThread)
|
|
{
|
|
// overflow & underflow check
|
|
fifo.bFF_HiWatermark = (fifo.CPReadWriteDistance > fifo.CPHiWatermark);
|
|
fifo.bFF_LoWatermark = (fifo.CPReadWriteDistance < fifo.CPLoWatermark);
|
|
|
|
// breakpoint
|
|
if (!isCPUThread)
|
|
{
|
|
if (fifo.bFF_BPEnable)
|
|
{
|
|
if (fifo.CPBreakpoint == fifo.CPReadPointer)
|
|
{
|
|
if (!fifo.bFF_Breakpoint)
|
|
{
|
|
INFO_LOG(COMMANDPROCESSOR, "Hit breakpoint at %i", fifo.CPReadPointer);
|
|
fifo.bFF_Breakpoint = true;
|
|
IncrementCheckContextId();
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (fifo.bFF_Breakpoint)
|
|
INFO_LOG(COMMANDPROCESSOR, "Cleared breakpoint at %i", fifo.CPReadPointer);
|
|
fifo.bFF_Breakpoint = false;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (fifo.bFF_Breakpoint)
|
|
INFO_LOG(COMMANDPROCESSOR, "Cleared breakpoint at %i", fifo.CPReadPointer);
|
|
fifo.bFF_Breakpoint = false;
|
|
}
|
|
}
|
|
|
|
bool bpInt = fifo.bFF_Breakpoint && fifo.bFF_BPInt;
|
|
bool ovfInt = fifo.bFF_HiWatermark && fifo.bFF_HiWatermarkInt;
|
|
bool undfInt = fifo.bFF_LoWatermark && fifo.bFF_LoWatermarkInt;
|
|
|
|
bool interrupt = (bpInt || ovfInt || undfInt) && m_CPCtrlReg.GPReadEnable;
|
|
|
|
isHiWatermarkActive = ovfInt && m_CPCtrlReg.GPReadEnable;
|
|
isLoWatermarkActive = undfInt && m_CPCtrlReg.GPReadEnable;
|
|
|
|
if (interrupt != interruptSet && !interruptWaiting)
|
|
{
|
|
u64 userdata = interrupt?1:0;
|
|
if (IsOnThread())
|
|
{
|
|
if (!interrupt || bpInt || undfInt || ovfInt)
|
|
{
|
|
if (!isCPUThread)
|
|
{
|
|
// GPU thread:
|
|
interruptWaiting = true;
|
|
CommandProcessor::UpdateInterruptsFromVideoBackend(userdata);
|
|
}
|
|
else
|
|
{
|
|
// CPU thread:
|
|
interruptSet = interrupt;
|
|
INFO_LOG(COMMANDPROCESSOR,"Interrupt set");
|
|
ProcessorInterface::SetInterrupt(INT_CAUSE_CP, interrupt);
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
CommandProcessor::UpdateInterrupts(userdata);
|
|
}
|
|
}
|
|
}
|
|
|
|
void ProcessFifoToLoWatermark()
|
|
{
|
|
if (IsOnThread())
|
|
{
|
|
while (!CommandProcessor::interruptWaiting && fifo.bFF_GPReadEnable &&
|
|
fifo.CPReadWriteDistance > fifo.CPLoWatermark && !AtBreakpoint())
|
|
Common::YieldCPU();
|
|
}
|
|
bProcessFifoToLoWatermark = false;
|
|
}
|
|
|
|
void ProcessFifoAllDistance()
|
|
{
|
|
if (IsOnThread())
|
|
{
|
|
while (!CommandProcessor::interruptWaiting && fifo.bFF_GPReadEnable &&
|
|
fifo.CPReadWriteDistance && !AtBreakpoint())
|
|
Common::YieldCPU();
|
|
}
|
|
bProcessFifoAllDistance = false;
|
|
}
|
|
|
|
void ProcessFifoEvents()
|
|
{
|
|
if (IsOnThread() && (interruptWaiting || interruptFinishWaiting || interruptTokenWaiting))
|
|
CoreTiming::ProcessFifoWaitEvents();
|
|
}
|
|
|
|
void Shutdown()
|
|
{
|
|
|
|
}
|
|
|
|
void SetCpStatusRegister()
|
|
{
|
|
// Here always there is one fifo attached to the GPU
|
|
m_CPStatusReg.Breakpoint = fifo.bFF_Breakpoint;
|
|
m_CPStatusReg.ReadIdle = !fifo.CPReadWriteDistance || AtBreakpoint() || (fifo.CPReadPointer == fifo.CPWritePointer);
|
|
m_CPStatusReg.CommandIdle = !fifo.CPReadWriteDistance || AtBreakpoint() || !fifo.bFF_GPReadEnable;
|
|
m_CPStatusReg.UnderflowLoWatermark = fifo.bFF_LoWatermark;
|
|
m_CPStatusReg.OverflowHiWatermark = fifo.bFF_HiWatermark;
|
|
|
|
INFO_LOG(COMMANDPROCESSOR,"\t Read from STATUS_REGISTER : %04x", m_CPStatusReg.Hex);
|
|
DEBUG_LOG(COMMANDPROCESSOR, "(r) status: iBP %s | fReadIdle %s | fCmdIdle %s | iOvF %s | iUndF %s"
|
|
, m_CPStatusReg.Breakpoint ? "ON" : "OFF"
|
|
, m_CPStatusReg.ReadIdle ? "ON" : "OFF"
|
|
, m_CPStatusReg.CommandIdle ? "ON" : "OFF"
|
|
, m_CPStatusReg.OverflowHiWatermark ? "ON" : "OFF"
|
|
, m_CPStatusReg.UnderflowLoWatermark ? "ON" : "OFF"
|
|
);
|
|
}
|
|
|
|
void SetCpControlRegister()
|
|
{
|
|
// If the new fifo is being attached, force an exception check
|
|
// This fixes the hang while booting Eternal Darkness
|
|
if (!fifo.bFF_GPReadEnable && m_CPCtrlReg.GPReadEnable && !m_CPCtrlReg.BPEnable)
|
|
{
|
|
CoreTiming::ForceExceptionCheck(0);
|
|
}
|
|
|
|
fifo.bFF_BPInt = m_CPCtrlReg.BPInt;
|
|
fifo.bFF_BPEnable = m_CPCtrlReg.BPEnable;
|
|
fifo.bFF_HiWatermarkInt = m_CPCtrlReg.FifoOverflowIntEnable;
|
|
fifo.bFF_LoWatermarkInt = m_CPCtrlReg.FifoUnderflowIntEnable;
|
|
fifo.bFF_GPLinkEnable = m_CPCtrlReg.GPLinkEnable;
|
|
|
|
if(m_CPCtrlReg.GPReadEnable && m_CPCtrlReg.GPLinkEnable)
|
|
{
|
|
ProcessorInterface::Fifo_CPUWritePointer = fifo.CPWritePointer;
|
|
ProcessorInterface::Fifo_CPUBase = fifo.CPBase;
|
|
ProcessorInterface::Fifo_CPUEnd = fifo.CPEnd;
|
|
}
|
|
|
|
if(fifo.bFF_GPReadEnable && !m_CPCtrlReg.GPReadEnable)
|
|
{
|
|
fifo.bFF_GPReadEnable = m_CPCtrlReg.GPReadEnable;
|
|
while(fifo.isGpuReadingData) Common::YieldCPU();
|
|
}
|
|
else
|
|
{
|
|
fifo.bFF_GPReadEnable = m_CPCtrlReg.GPReadEnable;
|
|
}
|
|
|
|
DEBUG_LOG(COMMANDPROCESSOR, "\t GPREAD %s | BP %s | Int %s | OvF %s | UndF %s | LINK %s"
|
|
, fifo.bFF_GPReadEnable ? "ON" : "OFF"
|
|
, fifo.bFF_BPEnable ? "ON" : "OFF"
|
|
, fifo.bFF_BPInt ? "ON" : "OFF"
|
|
, m_CPCtrlReg.FifoOverflowIntEnable ? "ON" : "OFF"
|
|
, m_CPCtrlReg.FifoUnderflowIntEnable ? "ON" : "OFF"
|
|
, m_CPCtrlReg.GPLinkEnable ? "ON" : "OFF"
|
|
);
|
|
|
|
}
|
|
|
|
// NOTE: The implementation of this function should be correct, but we intentionally aren't using it at the moment.
|
|
// We don't emulate proper GP timing anyway at the moment, so this code would just slow down emulation.
|
|
void SetCpClearRegister()
|
|
{
|
|
// if (IsOnThread())
|
|
// {
|
|
// if (!m_CPClearReg.ClearFifoUnderflow && m_CPClearReg.ClearFifoOverflow)
|
|
// bProcessFifoToLoWatermark = true;
|
|
// }
|
|
}
|
|
|
|
void Update()
|
|
{
|
|
while (VITicks > m_cpClockOrigin && fifo.isGpuReadingData && IsOnThread())
|
|
Common::YieldCPU();
|
|
|
|
if (fifo.isGpuReadingData)
|
|
Common::AtomicAdd(VITicks, SystemTimers::GetTicksPerSecond() / 10000);
|
|
}
|
|
} // end of namespace CommandProcessor
|